|Category||Logic => Decoder/Demultiplexers => Bipolar->LS Family|
|Description||64 Bit Fifo Memory|
|Company||Texas Instruments, Inc.|
|Datasheet||Download SN74LS228 datasheet
|× 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS
Independent Synchronous Inputs and Outputs 16 Words by 4 Bits Data Rates From to 10 MHz Fall-Through Time. 50 ns Typ Data Terminals Arranged for Printed-Circuit-Board Layout Expandable Using External Gating Packaged in Standard Plastic 300-mil DIPsdescription
This 64-bit memory is a low-power Schottky memory array organized as 16 words by 4 bits. It can be expanded in multiples + 1 words or 4n bits, or both (where n is the number of packages in the vertical array and m is the number of packages in the horizontal array), however some external gating is required (see Figure 1). For longer words using the SN74LS228, the IR signals of the first-rank packages and OR signals of the last-rank packages must be ANDed for proper synchronization. A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array at independent data rates. These FIFOs are designed to process data at rates from to 10 MHz in a bit-parallel format, word by word. Data is written into memory on a low-to-high transition at the load-clock (LDCK) input and is read out on a low-to-high transition at the unload-clock (UNCK) input. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect. Status of the FIFO memory is monitored by the input-ready (IR) and output-ready (OR) flags that indicate not-full and not-empty conditions. IR is high only when the memory is not full and the LDCK is low. OR is high only when the memory is not empty and UNCK is high. A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the IR and OR outputs. The SN74LS228 is characterized for operation from to 70°C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.× 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. This symbol is functionally accurate but does not show the details of implementation; for these, see the logic diagram. The symbol represents the memory if it were controlled by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0.× 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS
|Some Part number from the same manufacture Texas Instruments, Inc.|
|SN74LS228N ti SN74LS228, 16 X 4 Synchronous Fifo Memory With Open-collector Outputs|
|SN74LS22N ti SN74LS22, Dual 4-input Positive-nand Schmitt Triggers With Open Collector Outputs|
|SN74LS240 Octal Buffer And Line Driver With 3-state Outputs|
|SN74LS240DW ti SN74LS240, Octal Buffers And Line Drivers|
|SN74LS241 Octal Buffer And Line Driver With 3-state Outputs|
|SN74LS241DW ti SN74LS241, Octal Buffers And Line Drivers With 3-State Outputs|
|SN74LS242 Quad Bus Transceiver With 3-state Outputs|
|SN74LS242D ti SN74LS242, Quad Bus Transceivers|
|SN74LS243 Quad Bus Transceiver With 3-state Outputs|
|SN74LS243D ti SN74LS243, Quad Bus Transceivers|
|SN74LS244 Octal Buffer And Line Driver With 3-state Outputs|
|SN74LS244DBR ti SN74LS244, Octal Buffers And Line Drivers With 3-State Outputs|
|SN74LS245 Octal Line Transceiver With 3-state Outputs|
|SN74LS245DBR ti SN74LS245, Octal Bus Transceivers|
|SN74LS247 BCD to 7-segment Decoder/driver|
|SN74LS247D ti SN74LS247, Bcd-to-seven-segment Decoders/drivers|
|SN74LS248 Bcd-to-seven-segment Decoders/drivers|
|SN74LS248N ti SN74LS248, Bcd-to-seven-segment Decoders/drivers With Internal Pull-up Resistors|
|SN74LS24A Schmitt-trigger Positive NAND Gate And Inverter With Totem Pole Output|
|SN74LS24AD ti SN74LS24A, Schmitt-trigger Positive-nand Gates And Inverters With Totem-pole Outputs|
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