|Category||Logic => FIFOs => Synchronous FIFOs|
|Description||ti SN74LS224A, 16 X 4 Synchronous Fifo Memory With 3-State Outputs|
|Company||Texas Instruments, Inc.|
|Datasheet||Download SN74LS224AN datasheet
|× 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS
Independent Synchronous Inputs and Outputs 16 Words by 4 Bits Each 3-State Outputs Drive Bus Lines Directly Data Rates to 10 MHz Fall-Through Time 50 ns Typical Data Terminals Arranged for Printed Circuit Board Layout Expandable, Using External Gating Packaged in Standard Plastic (N) and Ceramic (J) 300-mil DIPs, and Ceramic Chip Carriers (FK)
A first-in, first-out (FIFO) memory is a storage device that allows data to be written to and read from its array at independent data rates. These FIFOs are designed to process data at rates to 10 MHz in a bit-parallel format, word by word.
The load clock (LDCK) normally is held low, and data is written into memory on the high-to-low transition of LDCK. The unload clock (UNCK) normally is held high, and data is read out on the low-to-high transition of UNCK. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect. Status of the FIFO memory is monitored by the IR and OR flags that indicate not-full and not-empty conditions. IR is high only when the memory is not full and LDCK is low. OR is high only when the memory is not empty and UNCK is high. A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting, with respect to the data inputs, and are at high impedance when the output-enable (OE) input is low. OE does not affect the IR and OR outputs. The SN74LS224A is characterized for operation from to 70°C. The SN54LS224A is characterized over the full military temperature range to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
The SN54LS224A and SN74LS224A 64-bit, low-power Schottky memories are organized as 16 words by 4 bits each. They can be expanded in multiples + 1 words or 4n bits, or both (where n is the number of packages in the vertical array and m is the number of packages in the horizontal array); however, some external gating is required. For longer words, the input-ready (IR) signals of the first-rank packages and output-ready (OR) signals of the last-rank packages must be ANDed for proper synchronization.description
× 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. This symbol is functionally accurate, but does not show the details of implementation; for these details, see the logic diagram. The symbol represents the memory if it were controlled by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0. Pin numbers shown are for the J and N packages.× 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS
|Related products with the same datasheet|
|Some Part number from the same manufacture Texas Instruments, Inc.|
|SN74LS224AN3 ti SN74LS224A, 16 X 4 Synchronous Fifo Memory With 3-State Outputs|
|SN74LS228 64 Bit Fifo Memory|
|SN74LS228N ti SN74LS228, 16 X 4 Synchronous Fifo Memory With Open-collector Outputs|
|SN74LS22N ti SN74LS22, Dual 4-input Positive-nand Schmitt Triggers With Open Collector Outputs|
|SN74LS240 Octal Buffer And Line Driver With 3-state Outputs|
|SN74LS240DW ti SN74LS240, Octal Buffers And Line Drivers|
|SN74LS241 Octal Buffer And Line Driver With 3-state Outputs|
|SN74LS241DW ti SN74LS241, Octal Buffers And Line Drivers With 3-State Outputs|
|SN74LS242 Quad Bus Transceiver With 3-state Outputs|
|SN74LS242D ti SN74LS242, Quad Bus Transceivers|
|SN74LS243 Quad Bus Transceiver With 3-state Outputs|
|SN74LS243D ti SN74LS243, Quad Bus Transceivers|
|SN74LS244 Octal Buffer And Line Driver With 3-state Outputs|
|SN74LS244DBR ti SN74LS244, Octal Buffers And Line Drivers With 3-State Outputs|
|SN74LS245 Octal Line Transceiver With 3-state Outputs|
|SN74LS245DBR ti SN74LS245, Octal Bus Transceivers|
|SN74LS247 BCD to 7-segment Decoder/driver|
|SN74LS247D ti SN74LS247, Bcd-to-seven-segment Decoders/drivers|
|SN74LS248 Bcd-to-seven-segment Decoders/drivers|
|SN74LS248N ti SN74LS248, Bcd-to-seven-segment Decoders/drivers With Internal Pull-up Resistors|
DSD1796 : 24-Bit Stereo Advanced Segment Audio DAC
THS1030I : 2.7 V to 5.5 v, 10-bit, 30 MSPS CMOS Analog-to-digital Converter
TPA741D : ti TPA741, Mono, Differential Input, Class-ab Audio Amplifier With Active High Shutdown, And Depop
UC1849 : Secondary Side Average Current Mode Controller
SN74AHC540PWRE4 : HEX Inverters
TPS2419DR : N+1 And ORing Power Rail Controller With Enable The TPS2419 controller, in conjunction with an external N-channel MOSFET, provides the reverse current protection of an ORing diode with the efficiency of a MOSFET. The TPS2419 can be used to combine multiple power supplies to a common bus in an N+1 c
AM26LV32ID : QUAD LINE RECEIVER, PDSO16 Specifications: Technology: RS422, BICMOS ; Device Type: Receiver ; Supply Voltage: 3.3V ; Operating Temperature: 0 to 70 C (32 to 158 F) ; Package Type: SOIC, PLASTIC, MS-012AC, SOIC-16 ; Pins: 16 ; Features: RoHS
COP8SAC520M7XXX : 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDSO20 Specifications: Life Cycle Stage: ACTIVE ; Clock Speed: 10 MHz ; ROM Type: MROM ; Supply Voltage: 4.5 to 5.5 volts ; I/O Ports: 16 ; Package Type: SOIC, Other, SOIC-20 ; Operating Range: Auto ; Pin Count: 20 ; Operating Temperature: -40 to 125 C (-40 to 257 F) ; Features: PWM
TMS320F28374SPZPT : 32-bit Microcontrollers - MCU Soprano
100351 : 100351 - Low Power Hex D-type Flip-flop. The 100351 contains six D-type edge-triggered, master/ slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and CPb (or both) go HIGH. The MR input overrides all other inputs and makes the Q outputs.
74ACT125 : CMOS/BiCMOS->AC/ACT Family->Advanced High Speed CM. Quad Bus Buffer (3-STATE).
74ALVCH32245 : HCMOS->ALVC->Advanced Low Voltage HCMOS. Low Voltage CMOS 32 Bit Bus Transceiver (3-STATE) With 3.6V Tolerant Inputs And Outputs.
74HC/HCT299 : CMOS/BiCMOS->HC/HCT Family. 8-bit Universal Shift Register; 3-state.
CD74AC175M : D-Type Flip-Flops. ti CD74AC175, Quad D-type Flip-flops With Reset. AC Types Feature to 5.5-V Operation and Balanced Noise Immunity 30% of the Supply Voltage Buffered Inputs Contains Four Flip-Flops With Double-Rail Outputs Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current Fanout 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit.
CD74FCT574E : D-Type (3-State) Flip-Flops. ti CD74FCT574, Bicmos FCT Interface Logic Octal Non-inverting D-type Flip-flops With 3-State Outputs.
CD74HC4538E : Monostable Multivibrators. ti CD74HC4538, High Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrators.
HCF4071 : HCF->CMOS 4000B Series. Quad 2 Input OR GATE. MEDIUM SPEED OPERATION : tPD = 60ns (TYP.) at VDD = 10V QUIESCENT CURRENT SPECIFIED 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT = 100nA (MAX) AT VDD 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD S FOR OF B SERIES CMOS DEVICES" The is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor.
HD74LV21A : . Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips.
IDT74FCT16827 : CMOS/BiCMOS->FCT/FCT-T Family. Fast CMOS 20-bit Buffer. MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tSK(o) (Output Skew) < 250ps Low input and output leakage 1µ A (max.) ESD > 2000V per MIL-STD-883, Method > 200V using machine model 0) 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch CERPACK packages Extended commercial range.
PCK2001R : PCK2001R; 533 MHZ I2C 1:6 Clock Buffer;; Package: SOT369-1 (SSOP16). Typically used to support four registered SDRAM DIMMs 16-pin SSOP package See PCK2001 for 48-pin 1:18 buffer part See PCK2001M for 28-pin 1:10 buffer part Operating frequency: - 533 MHz Optimized for 33 MHz, 66 MHz, 100 MHz and 133 MHz operation Part-to-part skew < 500 ps 175 ps skew outputs typical SYMBOL tPLH tPHL tr tf ICC PARAMETER Propagation.
SN54ALS259 : . 8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion With Storage Asynchronous Parallel Clear Active-High Decoder Enable/Disable Input Simplifies Expansion Expandable for n-Bit Applications Four Distinct Functional Modes Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic.
SN54LS422 : Retriggerable Monostable Multivibrators.
SN74ABT2241DB : Octal Buffers And Line/mos Drivers With 3-state Outputs. SN54ABT2241, SN74ABT2241 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-B TM BiCMOS Design Significantly Reduces Power Dissipation Typical VOLP (Output Ground Bounce) V at VCC = 25°C Package Options Include Plastic Small-Outline (DW),.
TC7MA257FK : VCX Equivalent. Function = Low Voltage Quad 2-Channel Multiplexer With 3.6 V Tolerant Inputs And Outputs ;; = Low Voltage Operation: VCC = 1.8~3.6 V High Speed Operation: TPD = 3.0 NS (max).
TC74HC181AP : HC/UH SERIES, 4-BIT ARITHMETIC LOGIC UNIT, PDIP24. s: Number of Bits: 4 ; Package Type: DIP, 0.300 INCH, PLASTIC, DIP-24 ; Logic Family: CMOS ; Number of Pins: 24 ; Propagation Delay: 270 ns ; Operating Temperature: -40 to 85 C (-40 to 185 F).
728980J : TELECOM, DIGITAL TIME SWITCH, PQCC44. s: Supply Voltage (VS): 5 volts ; Operating Temperature: -40 to 85 C (-40 to 185 F) ; Number of Pins: 44 ; Package Type: 0.650 X 0.650 INCH, 1.27 MM PITCH, PLASTIC, LCC-44.
935209050118 : LVT SERIES, TRIPLE 3-INPUT NAND GATE, PDSO14. s: Gate Type: NAND ; Supply Voltage: 3.3V ; Logic Family: BICMOS ; Inputs: 3 ; Propagation Delay: 6.2 ns ; Operating Temperature: -40 to 85 C (-40 to 185 F) ; Pin Count: 14 ; IC Package Type: Other, 3.90 MM, PLASTIC, MS-012AB, SOT-108-1, SO-14.