Details, datasheet, quote on part number: SN74LS221DBR
CategorySemiconductors => Logic => Specialty Logic => Monostable Multivibrator
Part familySN74LS221 Dual monostable multivibrators with Schmitt-trigger inputs
TitleMonostable Multivibrators
DescriptionDual monostable multivibrators with Schmitt-trigger inputs 16-SSOP 0 to 70
CompanyTexas Instruments, Inc.
DatasheetDownload SN74LS221DBR datasheet
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Operating Temperature Range(C)0 to 70
Technology FamilyLS
Schmitt TriggerNo
ICC @ Nom Voltage(Max)(mA)27
F @ Nom Voltage(Max)(Mhz)35
tpd @ Nom Voltage(Max)(ns)80
Output Drive (IOL/IOH)(Max)(mA)8/-0.4
Approx. Price (US$)0.40 | 1ku
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
Application notes
• Designing with the SN74LVC1G123 Monostable Multivibrator | Doc
• Designing with the SN54/74LS123 (Rev. A)
The Texas Instruments (TI) SN54/74LS123 dual retriggerable monostable multivibrator is a one-shot device capable of verylong output pulses and up to 100% duty cycle. The ?LS123 also features dc triggering from gated low-level active A andhigh-level active | Doc


Features, Applications

Dual Versions of Highly Stable SN54121 and SN74121 One Shots SN54221 and SN74221 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN54121 and SN74121 One Shots Pinout Is Identical to the SN74123, SN54LS123, and SN74LS123 Overriding Clear Terminates Output Pulse Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK) and Flat Packs (W), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs


The '221 and 'LS221 devices are monolithic dual multivibrators with performance characteristics virtually identical to those of the '121 devices. Each multivibrator features a negative-transitiontriggered input and a positive-transition-triggered input, either of which can be used as an inhibit input.

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with transition rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically V. A high immunity to VCC noise, typically V, is also provided by internal latching circuitry. Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration relative to the output pulse. Output pulse length can be varied from ns to the maximums shown in the above table by choosing appropriate timing components. With Rext 2 k and Cext 0, an output pulse typically ns is achieved, which can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics waveforms. Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.


Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing capacitance to 10 F) and more than one decade of timing resistance 30 k for the 40 k for the 70 k for the SN54LS221, and 100 k for the SN74LS221). Throughout these ranges, pulse width is defined by the relationship: tw(out) = CextRext In2 0.7 CextRext. In circuits where pulse cutoff is not critical, timing capacitance 1000 F and timing resistance as low 1.4 k can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held 5 V and free-air temperature is 25C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher duty cycles are available if a certain amount of pulse-width jitter is allowed. The variance in output pulse width from device to device typically is less than 0.5% for given external timing components. An example of this distribution for the '221 is shown in Figure 3. Variations in output pulse width versus supply voltage and temperature for the '221 are shown in Figures 4 and 5, respectively. Pin assignments for these devices are identical to those of the SN54LS123/SN74LS123 so that the or 'LS221 devices can be substituted for those products in systems not using the retrigger by merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed. The SN54221 and SN54LS221 are characterized for operation over the full military temperature range to 125C. The SN74221 and SN74LS221 are characterized for operation from to 70C.

FUNCTION TABLE (each monostable multivibrator) INPUTS CLR OUTPUTS

Pulsed-output patterns are tested during AC switching at 25C with Rext 2 k, and Cext = 80 pF. This condition is true only if the output of the latch formed by the two NAND gates has been conditioned to the logic 1 state prior to CLR going high. This latch is conditioned by taking either A high or B low while CLR is inactive (high).


This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, and W packages.

NOTE: Due to the internal circuit, the Rext/Cext terminal is never more positive than the Cext terminal.


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