|Category||Logic => Multivibrators/Oscillators|
|Description||Dual Monostable Multivibrators With Schmitt-trigger Inputs|
|Company||Texas Instruments, Inc.|
|Datasheet||Download SN74LS221DB datasheet
|SN74221, SN74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
Dual Versions of Highly Stable SN54121 and SN74121 One Shots SN54221 and SN74221 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN54121 and SN74121 One Shots Pinout Is Identical to the SN74123, SN54LS123, and SN74LS123 Overriding Clear Terminates Output Pulse Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK) and Flat Packs (W), and Standard Plastic (N) and Ceramic (J) 300-mil DIPsdescription
The '221 and 'LS221 devices are monolithic dual multivibrators with performance characteristics virtually identical to those of the '121 devices. Each multivibrator features a negative-transitiontriggered input and a positive-transition-triggered input, either of which can be used as an inhibit input.
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with transition rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically V. A high immunity to VCC noise, typically V, is also provided by internal latching circuitry. Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration relative to the output pulse. Output pulse length can be varied from ns to the maximums shown in the above table by choosing appropriate timing components. With Rext 2 k and Cext 0, an output pulse typically ns is achieved, which can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics waveforms. Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.SN74221, SN74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing capacitance to 10 µF) and more than one decade of timing resistance 30 k for the 40 k for the 70 k for the SN54LS221, and 100 k for the SN74LS221). Throughout these ranges, pulse width is defined by the relationship: tw(out) = CextRext In2 0.7 CextRext. In circuits where pulse cutoff is not critical, timing capacitance 1000 µF and timing resistance as low 1.4 k can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held 5 V and free-air temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher duty cycles are available if a certain amount of pulse-width jitter is allowed. The variance in output pulse width from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the '221 is shown in Figure 3. Variations in output pulse width versus supply voltage and temperature for the '221 are shown in Figures 4 and 5, respectively. Pin assignments for these devices are identical to those of the SN54LS123/SN74LS123 so that the or 'LS221 devices can be substituted for those products in systems not using the retrigger by merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed. The SN54221 and SN54LS221 are characterized for operation over the full military temperature range to 125°C. The SN74221 and SN74LS221 are characterized for operation from to 70°C.FUNCTION TABLE (each monostable multivibrator) INPUTS CLR OUTPUTS
Pulsed-output patterns are tested during AC switching at 25°C with Rext 2 k, and Cext = 80 pF. This condition is true only if the output of the latch formed by the two NAND gates has been conditioned to the logic 1 state prior to CLR going high. This latch is conditioned by taking either A high or B low while CLR is inactive (high).SN74221, SN74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, and W packages.
NOTE: Due to the internal circuit, the Rext/Cext terminal is never more positive than the Cext terminal.
|Some Part number from the same manufacture Texas Instruments, Inc.|
|SN74LS221DBR ti SN74LS221, Dual Monostable Multivibrators With Schmitt-trigger Inputs|
|SN74LS222AN ti SN74LS222A, 16 X 4 Synchronous Fifo Memory With 3-State Outputs|
|SN74LS224A 16 X 4 Synchronous First-in, First-out Memory With 3-state Outputs|
|SN74LS224AN ti SN74LS224A, 16 X 4 Synchronous Fifo Memory With 3-State Outputs|
|SN74LS228 64 Bit Fifo Memory|
|SN74LS228N ti SN74LS228, 16 X 4 Synchronous Fifo Memory With Open-collector Outputs|
|SN74LS22N ti SN74LS22, Dual 4-input Positive-nand Schmitt Triggers With Open Collector Outputs|
|SN74LS240 Octal Buffer And Line Driver With 3-state Outputs|
|SN74LS240DW ti SN74LS240, Octal Buffers And Line Drivers|
|SN74LS241 Octal Buffer And Line Driver With 3-state Outputs|
|SN74LS241DW ti SN74LS241, Octal Buffers And Line Drivers With 3-State Outputs|
|SN74LS242 Quad Bus Transceiver With 3-state Outputs|
|SN74LS242D ti SN74LS242, Quad Bus Transceivers|
|SN74LS243 Quad Bus Transceiver With 3-state Outputs|
|SN74LS243D ti SN74LS243, Quad Bus Transceivers|
|SN74LS244 Octal Buffer And Line Driver With 3-state Outputs|
|SN74LS244DBR ti SN74LS244, Octal Buffers And Line Drivers With 3-State Outputs|
|SN74LS245 Octal Line Transceiver With 3-state Outputs|
|SN74LS245DBR ti SN74LS245, Octal Bus Transceivers|
|SN74LS247 BCD to 7-segment Decoder/driver|
|SN74LS247D ti SN74LS247, Bcd-to-seven-segment Decoders/drivers|
UCC27423 : Dual 4-A MOSFET Driver With Enable
UCC3818D : Power Factor Correction IC's ti UCC3818, Bicmos Power Factor Preregulator
TLV7211 : The TLV7211 and TLV7211A are micropower CMOS comparators available in the space-saving SOT-23-5 package. This makes the comparators ideal for space- and weight-critical designs. The TLV7211A features an input offset voltage of 5 mV, and the TLV7211 features an input offset voltage of 15 mV. The m
LT1013DIDRG4 : DUAL Precision Operational Amplifiers
MSP430F2234TDAR : Mixed Signal Microcontroller
TLVH432QDBZRG4 : Low-voltage Adjustable Precision Shunt Regulators
LM3S617-EGZ50-C2T : Embedded - Microcontroller Integrated Circuit (ics) Internal Tray 3 V ~ 3.6 V; IC ARM CORTEX MCU 32KB 48VQFN Specifications: Program Memory Size: 32KB (32K x 8) ; RAM Size: 8K x 8 ; Number of I /O: 30 ; Package / Case: 48-VFQFN Exposed Pad ; Speed: 50MHz ; Oscillator Type: Internal ; Packaging: Tray ; Program Memory Type: FLASH ; EEPROM Size: - ; Core Processor: ARM® Cortex™-M3 ; Data Converters: A/D 6x10b
LM3S1N16-IQR50-C5 : Embedded - Microcontroller Integrated Circuit (ics) Internal Tray 1.08 V ~ 3.6 V; IC ARM CORTEX MCU 64KB 64-LQFP Specifications: Program Memory Size: 64KB (64K x 8) ; RAM Size: 12K x 8 ; Number of I /O: 33 ; Package / Case: 64-LQFP ; Speed: 50MHz ; Oscillator Type: Internal ; Packaging: Tray ; Program Memory Type: FLASH ; EEPROM Size: - ; Core Processor: ARM® Cortex-M3™ ; Data Converters: A/D 8x10b ; Core Size
LM3S5P36-IQR80-C5 : Embedded - Microcontroller Integrated Circuit (ics) Internal Tray 1.08 V ~ 1.32 V; IC ARM CORTEX MCU 64KB 64-LQFP Specifications: Program Memory Size: 64KB (64K x 8) ; RAM Size: 24K x 8 ; Number of I /O: 33 ; Package / Case: 64-LQFP ; Speed: 80MHz ; Oscillator Type: Internal ; Packaging: Tray ; Program Memory Type: FLASH ; EEPROM Size: - ; Core Processor: ARM® Cortex-M3™ ; Data Converters: A/D 8x10b ; Core Size
TRF370317IRGET : Rf Modulator Rf/if And Rfid; IC QUADRATURE MOD .4-4GHZ 24VQFN Specifications: Test Frequency: 2.14GHz ; Function: Modulator ; P1dB: 12dBm ; Current - Supply: 245mA ; Voltage - Supply: 4.5 V ~ 5.5 V ; RF Frequency: 400MHz ~ 4GHz ; LO Frequency: 400MHz ~ 4GHz ; Package / Case: 24-VFQFN Exposed Pads ; Packaging: Cut Tape (CT) ; Lead Free Status: Lead Free ; RoHS
INA3221AIRGVT : (ACTIVE) Triple Channel Shunt And Bus Voltage Monitor INA3221 (ACTIVE) Triple Channel Shunt and Bus Voltage Monitor
TMS320F28027PTR : IC MCU 32BIT 64KB FLASH 48LQFP Texas Instruments' F2802x Piccolo family of microcontrollers provides the power of the C28x core coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code and also provides a high level of analog integration.
74AC11010 : CMOS/BiCMOS->AC/ACT Family. Triple 3-input Positive-nand Gate. Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs These.
74V2T14CTR : Dual Schmitt Inverter. HIGH SPEED: tPD = 5.0ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC at TA=25°C TYPICAL HYSTERESIS: at VCC=4.5V POWER DOWN PROTECTION ON INPUT SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) at VCC = 4.5V BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) to 5.5V IMPROVED LATCH-UP IMMUNITY The is an advanced high-speed CMOS.
CD40193B : CMOS/BiCMOS->4000 Family. CMOS Presettable Up/down Counters (dual Clock With Reset).
CD54HC164F : ti CD54HC164, High Speed CMOS Logic 8-Bit Serial-in/parallel-out Shift Register.
DM74S163 : Bipolar->S Family. Synchronous 4-Bit Binary Counter With Synchronous Clear.
IDT74ALVCHR16543 : Bus Oriented Circuits. 3.3v CMOS 16-bit Registered Transceiver With 3-state Outputs And Bus-hold.
IDT74LVC16827A : Bus Oriented Circuits. 3.3v CMOS 20-bit Buffer With 5v Tolerant I/o. Typical tSK(o) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method > 200V using machine model = 0) VCC ± 0.3V, Normal Range VCC to 3.6V, Extended Range CMOS power levels (0.4µ W typ. static) All inputs, outputs, and I/O are 5V tolerant Supports hot insertion Available in SSOP, TSSOP, and TVSOP packages High Output Drivers: ±24mA Reduced.
MB2823BB : MB2823; Dual 9-bit D-type Flip-flop With Reset And Enable (3-State);; Package: SOT379-2 (QFP52).
SN5497J : Drivers/Multipliers. ti SN5497, Synchronous 6-Bit Binary Rate Multipliers.
SN54ALS169BFK : Synchronous 4-bit Up/down Binary Counters. Fully Synchronous Operation for Counting and Programming Internal Carry Look-Ahead Circuitry for Fast Counting Carry Output for n-Bit Cascading Fully Independent Clock Circuit Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs These synchronous 4-bit up/down binary.
SN74293 : Decade And 4-bit Binary Counters. PRODUCTION DATA information is current as of publication date. Products conform to s per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. .
SN74AHCT00 : CMOS/BiCMOS->HC/HCT Family. Quad 2-input Positive-nand Gates. Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 2000-V Human-Body Model 200-V Machine Model (A115-A) The 'AHCT00 devices perform the Boolean function or in positive logic. ORDERING INFORMATION TA PACKAGE QFN RGY PDIP N SOIC to 85°C SOP NS SSOP DB TSSOP PW TVSOP DGV CDIP to 125°C.
SN74HC11 : CMOS/BiCMOS->HC/HCT Family. Triple 3-input And Gate. D Wide Operating Voltage Range V D Outputs Can Drive to 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC The 'HC11 devices contain three independent 3-input AND gates. They perform the Boolean function or in positive logic. ORDERING INFORMATION TA PDIP N SOIC to 85°C SOP NS SSOP DB TSSOP PW CDIP to 125°C CFP W PACKAGE Tube Tape and reel.
A3P030-QN68YI : FPGA, 768 CLBS, 30000 GATES, QCC68. s: System Gates: 30000 ; Logic Cells / Logic Blocks: 768 ; Package Type: QFP, Other, 8 X 8 MM, 0.90 MM HEIGHT, 0.40 MM PITCH, QFP-68 ; Logic Family: CMOS ; Pins: 68 ; Operating Temperature: -40 to 85 C (-40 to 185 F) ; Supply Voltage: 1.5V.
935174380118 : HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16. s: Function: Decoder ; Supply Voltage: 4.5 ; Package Type: TSSOP, SOT-403-1, TSSOP-16 ; Logic Family: CMOS ; Number of Pins: 16 ; Propagation Delay: 225 ns ; Operating Temperature: -40 to 125 C (-40 to 257 F).