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Part: 74ACT11374NSR
Category:
Logic
-> Flip-Flops
-> D-Type (3-State) Flip-Flops
Description: ti 74ACT11374, Octal Edge-triggered D-type Flip-flops With 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download 74ACT11374NSR datasheet File size : 232 kB
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Datasheet text preview:
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS217A JULY 1987 REVISED APRIL 1996
D D D D D D D D D
Eight D-Type Flip-Flops in a Single Package 3-State Bus Driving True Outputs Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (NT)
DB, DW, OR NT PACKAGE (TOP VIEW)
1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
OE 1D 2D 3D 4D VCC VCC 5D 6D 7D 8D CLK
description
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the 74ACT11374 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. An output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state provides the capability to drive bus lines in a bus-organized system without need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The 74ACT11374 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each flip-flop) INPUTS OE L L L L L H CLK L H X D H L X X X X OUTPUT Q H L Q0 Q0 Q0 Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS217A JULY 1987 REVISED APRIL 1996
logic symbol
OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 24 13 23 22 21 20 17 16 15 14 EN C1 1D 1 2 3 4 9 10 11 12 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE CLK 24 13
1D
23
C1 1D
1
1Q
2D
22
C1 1D
2
2Q
3D
21
C1 1D
3
3Q
4D
20
C1 1D
4
4Q
5D
17
C1 1D
9
5Q
6D
16
C1 1D
10
6Q
7D
15
C1 1D
11
7Q
8D
14
C1 1D
12
8Q
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS217A JULY 1987 REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . . 1.7 W NT package . . . . . . . . . . . . . . . . . . . 1.3 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils, except for the NT package, which has a trace length of zero.
recommended operating conditions
MIN VCC VIH VIL VI VO IOH IOL Dt/Dv TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature 0 40 0 0 4.5 2 0.8 VCC VCC 24 24 10 85 MAX 5.5 UNIT V V V V V mA mA ns/V °C
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS217A JULY 1987 REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = 50 mA 50 mA VOH IOH = 24 mA 24 mA IOH = 75 mA{ IOL = 50 mA 50 mA VOL IOL = 24 mA 24 mA IOL = 75 mA{ VO = VCC or GND VI = VCC or GND VI = VCC or GND, One input at 3.4 V, VI = VCC or GND VO = VCC or GND IO = 0 Other inputs at GND or VCC TEST CONDITIONS CONDITIONS VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 4 ±0.5 ±0.1 8 0.9 0.1 0.1 0.36 0.36 MIN 4.4 5.4 3.94 4.94 TA = 25°C TYP MAX MIN 4.4 5.4 3.8 4.8 3.85 0.1 0.1 0.44 0.44 1.65 ±5 ±1 80 1 V V MAX UNIT
IOZ II ICC
mA mA mA
mA pF pF
DICC}
Ci
Co 5V 10 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended ranges of supply voltages and operating free-air temperature (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX fclock tw tsu th Clock frequency Pulse duration, CLK low or CLK high Setup time, data before CLK Hold time, data after CLK 0 9 3 5.5 55 MIN 0 9 3 5.5 MAX 55 UNIT MHz ns ns ns
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) TA = 25°C MIN TYP MAX 55 CLK Any Q Any Q Any Q 1.5 1.5 1.5 1.5 1.5 1.5 70 8.5 8.5 7.5 7.5 11 8 10.7 11.3 11 11 12.7 10 MIN 55 1.5 1.5 1.5 1.5 1.5 1.5 12.4 13 12.3 12.3 13.2 10.8 MAX UNIT MHz ns ns ns
OE OE
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS217A JULY 1987 REVISED APRIL 1996
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per flip-flop dissipation capacitance per flip flop Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF 50 pF, f = 1 MHz MHz TYP 107 96 UNIT pF
PARAMETER MEASUREMENT INFORMATION
2 × VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 × VCC GND
LOAD CIRCUIT Timing Input tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Data Input tsu 1.5 V 3V 1.5 V 0V th 3V 1.5 V 0V
3V Input 1.5 V tPLH In-Phase Output tPHL Out-of-Phase Output 50% VCC 50% VCC 1.5 V 0V tPHL VOH 50% VCC VOL tPLH VOH 50% VCC VOL
Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B)
3V 1.5 V tPZL tPLZ 50% VCC tPHZ 80% VCC VOH 20% VCC 1.5 V 0V
[ VC C
VOL
tPZH
50% VCC
[0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
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