|Category||Power Management => Supervisory Circuits => System Supervisors/Reset => Precision Reset|
|Description||Precision Supply-voltage Monitor And Reset Controller (Organized X8)|
|Company||Summit Microelectronics, Inc.|
|Datasheet||Download S93462 datasheet
FEATURES Precision Monitor & RESET Controller RESET and RESET Outputs Guaranteed RESET Assertion to VCC 1V 150ms Reset Pulse Width Internal 1.26V Reference with ±1% Accuracy ZERO External Components Required Memory 1K-bit Microwire Memory S93462 Internally Ties ORG Low 100% Compatible With all 8-bit Implementations Sixteen Byte Page Write Capability S93463 Internally Ties ORG High 100% Compatible With all 16-bit Implementations Eight Word Page Write Capability
OVERVIEW The S93462 and S93463 are precision power supervisory circuits providing both active high and active low reset outputs. Both devices have of E2PROM memory that is accessible via the industry standard microwire bus. The S93462 is configured with an internal ORG pin tied low providing a 8-bit byte organization and the S93463 is configured with an internal ORG pin tied high providing a 16-bit word organization. Both the S93462 and S93463 have page write capability. The devices are designed for a minimum 100,000 program/erase cycles and have data retention in excess of 100 years.
© SUMMIT MICROELECTRONICS, Inc. 2001 300 Orchard City Drive, Suite 131 Campbell, CA 95008 Telephone 408-378-6461 Fax 408-378-6586 www.summitmicro.com
During power-up, the reset outputs remain active until VCC reaches the VTRIP threshold. The outputs will continue to be driven for approximately 150ms after reaching VTRIP. The reset outputs will be valid so long as VCC is 1.0V. During power-down, the reset outputs will begin driving active when VCC falls below VTRIP. The reset pins are I/Os; therefore, the S93462/463 can act as a signal conditioning circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset time-out after detecting a low to high transition and the RESET# input will initiate a reset time-out after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a debounce/reset extender circuit. It should be noted the reset outputs are open drain. When used as outputs driving a circuit they need to be either tied high (RESET#) or tied to ground (RESET) through the use of pull-up or pull-down resistors. Refer to the applications aid section for help in determining the value of resistor to be used. Internally these pins are weakly pulled up (RESET#) and pulled down (RESET): therefore, if the signals are not being used the pins may be left unconnected. GENERAL OPERATION The a 1024-bit nonvolatile memory intended for use with industry standard microprocessors. The S93463 is organized as X16, seven 9-bit instructions control the reading, writing and erase operations of the device. The S93462 is organized as X8, seven 10-bit instructions control the reading, writing and erase operations of the device. The device operates on a single or 5V supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. See the Applications Aid section for detailed use of the ready busy status.
Pin Name DI DO VCC GND RESET/RESET# Function Chip Select Clock Input Serial Data Input Serial Data Output to 6.0V Power Supply Ground RESET I/O
APPLICATIONS The S93462/463 is ideal for applications requiring low voltage and low power consumption. This device provides microcontroller RESET control and can be manually resettable. RESET CONTROLLER DESCRIPTION The S93462/463 provides a precision reset controller that ensures correct system operation during brownout and power-up/-down conditions. It is configured with two open drain reset outputs; pin is an active high output and pin is an active low output.
The format for all instructions is: one start bit; two op code bits and either six (x16) or seven (x8) address or instruction bits. Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the S93462/463 will come out of the high impedance state and, will first output an initial dummy zero bit, then begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay or tPD1). Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tCSMIN). The falling edge of CS will start automatic erase and write cycle to the memory location specified in the instruction. The ready/busy status of the S93462/463 can be determined by selecting the device and polling the DO pin. Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tCSMIN). The falling edge of CS will start the auto erase cycle of the selected memory location. The ready/busy status of the S93462/463 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical "1" state.
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