|Category||Memory => EPROM => 8 Mb|
|Description||Address Latched 256k 32k X 8 uv EPROM And OTP EPROM|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download M87C257-90XF1X datasheet
INTEGRATED ADDRESS LATCH FAST ACCESS TIME: 45ns LOW POWER "CMOS" CONSUMPTION: Active Current 30mA Standby Current 100µA PROGRAMMING VOLTAGE: 12.75V ELECTRONIC SIGNATURE for AUTOMATED PROGRAMMING TIMES of AROUND 3sec. (PRESTO II ALGORITHM)
Figure 1. Logic Diagram DESCRIPTION The is a high speed 262,144 bit UV erasable and electrically programmable EPROM. The M87C257 incorporates latches for all address inputs to minimize chip count, reduce cost, and simplify the design of multiplexed bus systems. The Window Ceramic Frit-Seal Dual-in-Line package has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M87C257 is offered in Plastic Leaded Chip Carrier, package.
E G ASVPP VCC VSS Address Inputs Data Outputs Chip Enable Output Enable Address Strobe / Program Supply Voltage Ground
Parameter Ambient Operating Temperature Under Bias Storage Temperature Input or Output Voltages (except A9) Supply Voltage A9 Voltage Program Supply Voltage
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
DEVICE OPERATION The modes of operation of the M87C257 are listed in the Operating Modes. A single power supply is required in the read mode. All inputs are TTL levels except for VPP and on A9 for Electronic Signature.
Read Mode The M87C257 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should
Mode Read (Latched Address) Read (Applied Address) Output Disable Program Verify Program Inhibit Standby Electronic Signature- Q7 Data Out Data Out Hi-Z Data In Data Out Hi-Z Codes
Identifier Manufacturer's Code Device Code A0 VIL VIH Q0 0 Hex Data 20h 80h
be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable (AS = VIH) or latched (AS = VIL), the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. The M87C257 reduces the hardware interface in multiplexed address-data bus systems. The processor multiplexed bus (AD0-AD7) may be tied to the M87C257's address and data pins. No separate address latch is needed because the M87C257 latches all address inputs when AS is low. Standby Mode The M87C257 has a standby mode which reduces the active current from to 100µA (Address Stable). The M87C257 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.
Two Line Output Control Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device.
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