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Details, datasheet, quote on part number:M29F100BT90M1
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Datasheet text preview:
M29F100BT M29F100BB
1 Mbit (12 8Kb x8 or 64K b x16, Boot Blo ck) Singl e Supply Flash Memory
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SING LE 5V±10% SUPPLY VOLTAGE for PROG RAM, ERASE and READ OPERATIONS ACCESS TIME: 45ns PROG RAMMING TIME 8µs per Byte/Word typical 5 MEMORY BLOCKS 1 Boot Block (Top or Bottom Location) 2 Parameter and 2 Main Blocks
1 44
s s
s
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PROG RAM/ERASE CONTROLLER Embedded Byte/Word Program algorithm Embedded Multi-Block/Chip Erase algorithm Status Register Polling and Toggle Bits Ready/Busy Output Pin
TSOP 48 (N) 12 x 20mm
SO 44 (M)
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ERASE SUSPEND and RESUME MODES Read and Program another Block during Erase Suspend
Figure 1. Logic Diagram
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UNLOCK BYPASS PROGRAM COMMAND F aster Production/Batch Programming TEMPORARY BLOCK UNPROTECTION MODE LOW PO WER CONSUMPTION Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION Defectivity below 1 ppm/year ELECTRONIC SIGNATURE M anufacturer Code: 0020h T op Device Code M29F100BT: 00D0h Bottom Device Code M29F100BB: 00D1h
A0-A15 W E G RP
VCC
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16
15 DQ0-DQ14 DQ15A1 M29F100BT M29F100BB BYTE RB
s
s
s
s
VSS
AI02916
July 2000
1/22
M29F100BT, M 29F10 0 BB
Figure 2. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB NC NC A7 A6 A5 A4 A3 A2 A1 1 48 NC BYTE VSS DQ15A1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
Figure 3. SO Connections
12 13
M29F100BT M29F100BB
37 36
NC RB NC A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 M29F100BT 12 M29F100BB 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
RP W A8 A9 A10 A11 A12 A13 A14 A15 NC BYTE VSS DQ15A1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
24
25
AI02917
AI02918
Table 1. Signal Names
A0-A15 DQ0-DQ7 DQ8-DQ1 4 DQ15A1 E G W RP RB BYTE VCC VSS NC 2/22 Address Inputs Dat a Inputs/Outputs Dat a Inputs/Outputs Dat a Input/Output or Address I nput Chip Enable Out put E nable Wr ite E nable Reset/Block Temporary Unprotec t Ready/Busy O utput Byte /Word Organization S elect Supply Voltage Gro und Not Connected Inte rnally
SUMMARY DESCRIPTION The M29F100B is a 1 Mbit (128Kb x8 or 64Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in t he same way as a RO M or EPROM. The M29F100B i s fully backward compatible wit h the M29F100. The memory is divided i nto blocks that can be erased independently s o i t i s possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from m odifying t he memory. Program and Erase commands are written to the Command Interface of the m emory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required t o update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The c ommand set required to control t he memory is consistent with JEDEC standards.
M 29F1 00B T , M 29F10 0B B
Table 2. Absolute Maximum Ratings (1)
Symb ol Parameter Ambient Operating Temperature (Temperature Range Option 1) TA Ambient Operating Temperature (Temperature Range Option 6) Ambient Operating Temperature (Temperature Range Opti on 3) TB IAS TS TG VIO (2) VCC V ID Temperature U nder Bias Storage Temperature Input or Output Voltage Supply Voltage Identification Voltage Value 0 to 70 40 t o 85 40 to 125 50 to 125 65 to 150 0.6 to 6 0.6 to 6 0.6 to 13.5 Unit °C °C °C °C °C V V V
Note: 1. Except for the rating " Operating T emperature R ange", stresses above those liste d in the Table "A bsolute Maximum R atings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above t hose indicated in t he Operating sections of t his s pecification is not impl ied. Exposure t o A bsolute M aximum R ating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot t o 2V during tr ansition and for les s t han 20ns during tr ansitions.
The blocks in the memory are asymmetrically arranged, see Tables 3 and 4, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and t he remaining 32K is a small M ain Block where the application may be stored. Table 3. Top Boot Block Addresses M29F100BT
# 4 3 2 1 0 Siz e (Kbyte s) 16 8 8 32 64 Address Rang e (x8) 1C000h-1FFFF h 1A000h-1BFFF h 18000h-19FFFh 10000h-17FFFh 00000h-0FFFF h Addres s Range (x16) E000h-FFFFh D000h-DFFFh C000h-CFFFh 8000h-BFFFh 0000h-7FFFh
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple c onnection to most microprocessors, often without additional logic. The memory is offered in TSOP48 (12 x 20mm) and SO44 packages and it is supplied with all the bits erased (set to '1').
Table 4. Bottom Boot Bl ock Addresses M29F100BB
# 4 3 2 1 0 Siz e (K byte s) 64 32 8 8 16 Addre ss Rang e (x8) 10000h-1FFFF h 08000h-0FFFF h 06000h-07FFF h 04000h-05FFF h 00000h-03FFF h Address Range (x16) 8000h-FFFFh 4000h-7FFFh 3000h-3FFFh 2000h-2FFFh 0000h-1FFFh
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