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Details, datasheet, quote on part number:M295V100-T90N3R
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Datasheet text preview:
M29F100T M29F100B
1 Mbit (128Kb x8 or 64Kb x16, Boot Block) Single Supply Flash Memory
5V ± 10% SUPPLY VOLTAGE f or PROGRAM, ERASE and READ OPERATIONS FAST ACCESS TIME: 70ns FAST PROGRAMMING TIME 10µs by Byte / 16µs by Word typical PROGRAM/ERASE CONTROLLER (P/E.C.) Program Byte-by-Byte or Word-by-Word Status Register bits and Ready/Busy Output MEMORY BLOCKS Boot Block (Top or Bottom location) Parameter and Main blocks BLOCK, MULTI-BLOCK and CHIP ERASE MULTI-BLOCK PROTECTION/TEMPORARY UNPROTECTION MODES ERASE SUSPEND and RESUME MODES Read and Program another Block during Erase Suspend LOW POWER CONSUMPTION Stand-by and Automatic Stand-by 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION Defectivity below 1ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code, M29F100T: 00D0h Device Code, M29F100B: 00D1h DESCRIPTION The M29F100 is a non-volatile memory that may be erased electrically at the block or chip level a nd programmed in-system on a Byte-by-Byte or Wordby-Word basis using only a single 5V VC C supply. For Program and Erase operations the necessary high voltages are generate d internally. The device can also be programmed in standard programmers. The array matrix organisation al lows each block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against programing and erase on programming equipment, and temporarily unprotect ed to make changes in the application . Each block can be programmed and erased over 100,000 cycles.
July 1998
44
1
T SOP48 (N) 12 x 20 mm
SO44 (M)
Figure 1. Logic Diagram
VCC
16 A0-A15 W E G RP M29F100T M29F100B
15 DQ0-DQ14 DQ15A1 BYTE RB
VSS
AI01974
1/30
M29F100T, M29F100B
Figure 2A. TSOP Pin Connections
A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB NC NC A7 A6 A5 A4 A3 A2 A1 1 48 NC BYTE VSS DQ15A1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
Figure 2B. TSOP Reverse Pin Connections
NC BYTE VSS DQ15A1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 1 48 A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB NC NC A7 A6 A5 A4 A3 A2 A1
12 13
M29F100T M29F100B (Normal)
37 36
12 13
M29F100T M29F100B (Reverse)
37 36
24
25
AI01975
24
25
AI01976
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Figure 2C. SO Pin Connections
Table 1. Signal Names
A0-A15 Address Inputs Data Input/Outputs, Command Inputs Data Input/Outputs Data Input/Output or Address Input Chip Enable Output Enable Write Enable Reset / Block Temporary Unprotect Ready/Busy Output Byte/Word Organisation Supply Voltage Ground
NC RB NC A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 M29F100T 12 M29F100B 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
RP W A8 A9 A10 A11 A12 A13 A14 A15 NC BYTE VSS DQ15A1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
DQ0-DQ7 DQ8-DQ14 DQ15A1 E G W RP RB B YTE VCC VSS
AI01977
Warning: NC = Not Connected. 2/30
M29F100T, M29F100B
Table 2 . Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO
(2)
Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltages Supply Voltage
(2) (3)
Value 40 to 125 50 to 125 65 to 150 0.6 to 7 0.6 to 7 0.6 to 13.5
Unit °C °C °C V V V
VCC V(A9, E, G, RP)
A9, E, G, RP Voltage
Notes: 1. Except for the rating "Operating Temperature Range", s tresses above those lis ted in the Table "Absolute Maximum Ra tings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this s pecification is not i mplied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot t o 2V during t ransition and for less than 20ns. 3. Depends on range.
DESCRIPTION (Cont'd) Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection status, Programming, Block and Chip Erase, Erase Suspend and Resume are written to the device in cycles of commands to a Command Interface using standard microprocessor write timings. The device is offered in TSOP48 (12 x 20mm) and SO44 packages . Both normal and reverse pinouts are available for the TSOP48 package. Organisation The M29F100 is organised as 128Kb x8 or 64Kb x16 bits selectable by the B YTE signal. When B YTE is Low the Byte-wide x8 organisation is selected and the address lines are DQ15A1 and A0-A15. The Data Input/Output signal DQ15A1 acts as address line A1 which selects the lower or upper Byte of t he memory word for output on DQ0-DQ7, DQ8-DQ14 remain at High impedance . When B YTE is High t he memory uses the address inputs A0-A15 and the Data Input/Outp uts DQ0DQ15. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. A Reset/Block Temporary Unprotection RP t ri-level input provides a hardware reset when pulled Low, and when held High (at VID) temporarily unprotect s blocks previously protected allowing them to be programed and erased. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, and DQ6 and DQ2 provide Toggle signals to indicate the state of
the P/E.C operations. A Ready/Busy RB output indicates the completion of the internal algorithms. Memory Blocks The devices feature asymmetrically blocked architecture p roviding system memory integration. Both M29F100T and M29F100B devices have a n array of 5 blocks, one Boot Block of 16 KBytes or 8 KWords, two Parameter Blocks of 8 KBytes or 4 KWords, on e Ma in Bl ock o f 32 KBytes or 16 KWords and one Main Blocks of 64 KBytes or 32 KWords. The M29F100T has the Boot Block at the t o p o f t h e me mo r y a d d re s s s p a c e a n d t h e M29F100B locates the Boot Block starting at the bottom. The memory maps are showed in Figure 3. Each block can be erased separately, any combination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase oper a tio ns a re man aged au toma tical ly by t he P/E.C. The block erase operation can be suspended in order to read from or program to any block not being ersased, and then resumed. Block protection provides additional data security. Each block can be separately protected or unprotected against Program or Erase on programming equipment. All previously protected blocks can be temporarily unprote cted in the application. Bus Operations The following operations can be performed using the appropriate bus cycles: Read (Array, Electronic Signature, Block Protection Status), Write command, Output Disable, Standby, Reset, Block Prot e c t i o n , U n p r o t e c t i o n , P r o t e c t i o n V e r i f y, Unprotection Verify and Block Temporary Unprotection. See Tables 4 and 5.
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