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Details, datasheet, quote on part number:M28W160BTB100N1T
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Datasheet text preview:
M28W160BT M28W160BB
16 Mbit (1Mb x16, Boot Block) Low Voltage Flash Memory
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SUPPLY VOLTAGE VDD = 2.7V to 3.6V: for Program, Erase and Rea d VDDQ = 1.65V or 2.7V: Input/Output option VPP = 12V: optional Supply Voltage for fast P r ogram
µBGA
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ACCESS TIME 2.7V to 3.6V: 90ns 2.7V to 3.6V: 100ns
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PROGRAMMING TIME: 10µs typical Double Word Programming Option
TSOP48 (N) 12 x 20mm
µBGA46 (GB) 8 x 6 solder balls
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PROGRAM/ER ASE CONTROLLER (P/E.C.) COMMON FLASH INTERFACE 64 bit Security Code MEMOR Y BLOCKS Parameter Blocks (Top or Bottom location) Main Blocks Figure 1. Logic Diagram
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BLOCK PROTECTION on TWO PARAMETER BLOCKS W P for Block Protection
20 A0-A19 W E G RP WP
VDD VDDQ VPP 16 DQ0-DQ15
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AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS of DATA RETENTION Defectivity below 1ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M28W160BT: 90h Bottom Device Code, M28W160BB: 91h
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M28W160BT M28W160BB
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VSS
AI02628
May 2000
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M28W160BT, M28W160BB
Figure 2. µBGA Connections (Top view through package)
1 2 3 4 5 6 7 8
A
A13
A11
A8
VPP
WP
A19
A7
A4
B
A14
A10
W
RP
A18
A17
A5
A2
C
A15
A12
A9
A6
A3
A1
D
A16
DQ14
DQ5
DQ11
DQ2
DQ8
E
A0
E
VDDQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
VSS
F
VSS
DQ7
DQ13
DQ4
VDD
DQ10
DQ1
G
AI02629
Figure 3. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP VPP WP A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 A16 VDDQ VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
Table 1. Signal Names
A0-A19 DQ0-DQ7 DQ8-DQ15 E G W RP WP VDD VDDQ VPP VSS NC Address Inputs Data Input/Output, Command Inputs Data Input/Output Chip Enable Output Enable Write Enable Reset Write Protect Supply Voltage Power Supply for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Not Connected Internally
12 M28W160BT 37 13 M28W160BB 36
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AI02630
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M28W 160BT, M28W160BB
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO VDD, VDDQ VPP Parameter Ambient Operating Temperature (2) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Program Voltage Value 40 to 85 40 to 125 55 to 155 0.6 to VDDQ+0.6 0.6 to 4.1 0.6 to 13 Unit °C °C °C V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range.
DESCRIPTION The M28W160B is a 16 Mbit non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a Word-byWord basis. The device is offered in the TSOP48 (10 x 20mm) and the µBGA46, 0.75mm ball pitch packages. When shipped, all bits of the M28W160B are in the `1' state. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Each block can be programmed and erased over 100,000 cycles. V DDQ allows to drive the I/O pin down to 1.65V. An optional 12V VPP power supply is provided to speed up the program phase at customer production line environment. An internal Command Interface (C.I.) decodes the instructions to access/modify the memory content. The Program/Erase Controller (P/E.C.) automatically executes the algorithms taking care of the timings necessary for program and erase operations. Verification is performed too, unburdening the microcontroller, while the Status Register tracks the status of the operation. The following instructions are executed by the M28W160B: Read Array, Read Electronic Signature, Read Status Register, Clear Status Register, Program, Double Word Program, Block Erase, Program/Erase Suspend, Program/Erase Resume and CFI Query.
Organisation The M28W160B is organised as 1 Mbit by 16 bits. A0-A19 are the address lines; DQ0-DQ15 are the Data Input/Output. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. The Program and Erase operations are managed automatically by the P/E.C. Block protection against Program or Erase provides additional data security. The upper two (or lower two) parameter blocks can be protected to secure the code content of the memory. WP controls protection and unprotection operations. Mem ory Blocks The device features an asymmetrical blocked architecture. The M28W160B has an array of 39 blocks: 8 Parameter Blocks of 4 KWord and 31 Main Blocks of 32 KWord. M28W160BT has the Parameter Blocks at the top of the memory address space while the M28W160BB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Tables 3 and 4. The two upper parameter block can be protected from accidental programming or erasure using WP. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed.
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