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Details, datasheet, quote on part number:M24C02REA6T
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Datasheet text preview:
M24C16, M24C08 M24C04, M24C02, M24C01
16/8/4/2/1 Kbit Serial I²C Bus EEPROM
s
Two Wire I2C Serial Interface Supports 400 kHz Protocol Single Supply Voltage: 4.5V to 5.5V for M24Cxx 2.5V to 5.5V for M24Cxx-W 1.8V to 3.6V for M24Cxx-R
s
8 1
PSDIP8 (BN) 0.25 mm frame
8 1
SO8 (MN) 150 mil width
s s s s s s s s
Hardware Write Control BYTE and PAGE WRITE (up to 16 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior 1 Million Erase/Write Cycles (minimum) 40 Year Data Retention (minimum)
8
SBGA
1
TSSOP8 (DW) 169 mil width SBGA5 (EA) 75 mil width
DESCRIPTION These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 2048/1024/512/256/128 x 8 bit (M24C16, M24C08, M24C04, M24C02, M24C01), and operate with a power supply down to 2.5 V (for the -W version of each device), and down to 1.8 V (for the -R version of each device). The M24C16, M24C08, M24C04, M24C02, M24C01 are available in Plastic Dual-in-Line, Plastic Small Outline and Thin Shrink Small Outline packages. The M24C16-R is also available in a chip-scale (SBGA) package.
Figure 1. Logic Diagram
VCC
3
Table 1. Signal Names
E0, E1, E2 SDA Chip Enable Inputs Serial Data/Address Input/ Output Serial Clock Write Control Supply Voltage Ground
E0-E2 SCL WC M24Cxx
SDA
SCL WC V CC VSS
VSS
AI02033
May 2000
1/20
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 2A. DIP Connections
M24Cxx 16Kb /8Kb /4Kb /2Kb /1Kb NC / NC / NC / E0 / E0 NC / NC / E1 / E1 / E1 NC / E2 / E2 / E2 / E2 VSS
1 2 3 4
8 7 6 5
VCC WC SCL SDA
AI02034D
Note: 1. NC = Not Connected
Figure 2B. SO Connections
M24Cxx 16Kb /8Kb /4Kb /2Kb /1Kb NC / NC / NC / E0 / E0 NC / NC / E1 / E1 / E1 NC / E2 / E2 / E2 / E2 VSS
1 2 3 4
8 7 6 5
VCC WC SCL SDA
AI02035D
Note: 1. NC = Not Connected
Figure 2C. Standard-TSSOP Connections
M24Cxx 16Kb /8Kb /4Kb /2Kb /1Kb NC / NC / NC / E0 / E0 NC / NC / E1 / E1 / E1 NC / E2 / E2 / E2 / E2 VSS
1 2 3 4
8 7 6 5
VCC WC SCL SDA
AI02036D
Note: 1. NC = Not Connected
Figure 2D. SBGA Connections (top view, marking side, with balls on the underside)
M24C16
WC
VCC Ball "1" SDA
SCL
VSS
AI02796E
2/20
M24C16, M24C08, M24C04, M24C02, M24C01
Table 2. Absolute Maximum Ratings 1
Symbol TA TSTG Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering Input or Output range Supply Voltage Electrostatic Discharge Voltage (Human Body model2) PSDIP8: 10 sec SO8: 40 sec TSSOP8: 40 sec SBGA5: t.b.c. Value -40 to 125 -65 to 150 260 215 215 t.b.c. -0.6 to 6.5 -0.3 to 6.5 4000 Unit °C °C
TLEAD
°C
VIO VCC VESD
V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100 pF, 1500 )
These memory devices are compatible with the I2C memory standard. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 4-bit unique Device Type Identifier code (1010) in accordance with the I2C bus definition. The memory behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit (as described in Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ. Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is held active until the V CC voltage has reached the POR threshold value, and all operations are
Figure 3. Maximum R L Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC 20 Maximum RP value (k) 16 RL 12 8 4 0 10 100 CBUS (pF)
AI01665
RL
SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS
CBUS 1000
3/20
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