|Category||Analog & Mixed-Signal Processing|
|Description||Pal CCD Delay Line|
|Company||Sanyo Semiconductor Corporation|
|Datasheet||Download LC89973M datasheet
The is a CCD delay line for PAL television systems. It incorporates a comb filter for chrominance signal and a 1H delay line for luminance signal.
Built-in peripheral circuits allow applications to be constructed with a minimum number of external components. Positive-phase signal input/positive-phase signal output (luminance signal)
Two CCD shift registers (for chrominance and luminance signals) CCD drive circuits CCD stage count switching circuit CCD signal adder Auto-bias circuit Sync tip clamping circuit (luminance signal) Center-bias circuit (chrominance signal) Sample-and-hold circuit PLL 3 × frequency multiplier fsc clock output circuit RD voltage generatorFeatures
5 V single-voltage power supply Built-in PLL 3 × frequency multiplier circuit allows 3 fsc operation from an fsc (4.43 MHz) input. Control pin switchable to handle PAL/GBI and 4.43 MHz NTSC systems. Built-in chrominance signal crosstalk exclusion comb filter features high precision comb characteristics in an adjustment-free circuit.Specifications
Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max Pd max Topr Tstg Conditions Ratings to +150 Unit mW °CSANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Parameter Supply voltage Clock input amplitude Clock frequency Clock signal input amplitude Luminance signal input amplitude Symbol VDD VCLK FCLK VIN-C VIN-Y Sine wave Conditions min 4.75 300 typ max Unit V mVp-p MHz mVp-pElectrical Characteristics at VDD = 25°C, FCLK = 4.43361875 MHz, VCLK = 500 mVp-p
Parameter Symbol TDC-1 TDC-2 Switch states SW3 b Conditions min typ max Unit
Chrominance System Characteristics (with no Y-IN input) Pin voltage (input) a, b mVrms 2.8 V
Luminance System Characteristics (with or C-IN2 input) Pin voltage (input) c, b mVrms deg 2.5 V
Test Conditions 1. Supply current with no signal input. 2. C-OUT voltage (center bias voltage) with no signal input. 3. Measure the C-OUT output with 350 mVp-p sine wave signals input to C-IN1 and C-IN2. GVC = 20 log C-OUT output [mVp-p] [dB] 350 [mVp-p]
|Some Part number from the same manufacture Sanyo Semiconductor Corporation|
|LC89975M Pal-format Delay Line|
|LC89977M CCD Delay Line For Pal|
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