|Description||1H Delay Line For Pal System|
|Company||Sanyo Semiconductor Corporation|
|Datasheet||Download LC89950 datasheet
The an IC that provides 1H delay processing for color difference signals used in PAL and SECAM format TV. The LC89950 has two CCD systems, one for the R-Y and one for the B-Y signal, and drives these CCDs with a 4-MHz clock generated within the IC. It uses a sandcastle-shaped three-value input clock with H (64 µs) period. Auto-bias and input clamping circuits 4-MHz output circuitFeatures
5-V single-voltage power supply Two input and output systems, one each for R-Y and BY signals Takes a sandcastle pulse (SCP) as the input clock, and converts that to a burst gate pulse (BGP) signal internally. Generates the CCD drive pulses (4 MHz) from the input clock using a PLL circuit. Uses BGP as clamp pulses and clamps the no signal section (back porch) once every horizontal scan period. The output signal is in-phase with the input signal
Two on-chip 254.5-bit CCD shift registers CCD drive circuits Sample-and-hold circuit Burst gate pulse detection circuit 256 × PLL circuitSpecifications
Parameter Supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD Pd max Topr Tstg Conditions Ratings to +125 Unit mW °C
Parameter Supply voltage Input signal amplitude Symbol VDD VINPP(R-Y) VINPP(B-Y) Conditions min 4.75 typ 5.0 500 max 5.25 700 Unit V mVSANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
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Switch States Parameter Current drain Output pin voltage (pin 1) Output pin voltage (pin 3) Input pin voltage (pin 7) Input pin voltage (pin 5) Voltage gain Differential voltage gain Frequency characteristics Symbol SW1 IDD VOUT (R-Y) VOUT (B-Y) VIN (R-Y) VIN (B-Y) GV (R-Y) GV (B-Y) GV Gf (R-Y) Gf (B-Y) +L6 (R-Y) +L6 (B-Y) L6 (R-Y) L6 (B-Y) Lclk (R-Y) Lclk (B-Y) No (R-Y) No (B-Y) ZOUT (R-Y) ZOUT (B-Y) Td (R-Y) Td (B-Y) a/b a SW3 a/b SW4 a/b Test conditions min typ max Unit mA dB mVrms µs
Parameter Input frequency*1 Input pulse width High level*2 Mid level*3 Low level Symbol Fscp TW bgp Vhigh Vmid Vlow Conditions min typ max Unit kHz µs V
Notes: 1. Indicates the synchronization range for the PLL circuit. The delay time changes with the input frequency. 2. Vhigh is the minimum value between c and d. 3. Vmid is the maximum value between a and b and between e and f.
LC89950 Test Conditions 1. Measure the power-supply current when no input signal is supplied. 2. Measure the pin voltages on each pin when no input signal is supplied. 3. Let VOUT be the OUT pin signal amplitude when 200-kHz 350-mVp-p sine wave is input. Then, the voltage gain (GV) for each of the R-Y and B-Y I/O systems is given by: VOUT [mVp-p] = 20log [dB] 350 [mVp-p] The R-Y and B-Y voltage gains (GV) are: | GV (R-Y) GV (B-Y)| 4. Let V1 be the OUT pin output when 100-kHz 200-mVp-p sine wave is input. Let V2 be the OUT pin output when 1-MHz 200-mVp-p sine wave is input. V2 [mVp-p] = 20log [dB] V1 [mVp-p] 5. Input a 5-stage step waveform (350 mVp-p) and measure the levels a and b in the output signals. Perform those measurements for both positive phase and inverted signal inputs. <Positive phase signal input>
6. Measure the noise spectrum of the output signal when no input is supplied and read the 4-MHz peak. 7. Pass the output signal through a 2-MHz low-pass filter and a 100-kHz high-pass filter. Then, measure that output with a noise meter, when no input signal is supplied. Use a 2-MHz low-pass filter with an attenuation 4-MHz. 8. Input 200-kHz 350-mVp-p sine wave. Let V1 be the OUT pin output when SW2 is set to a. Let V2 be the OUT pin output when SW2 is set b. V1 [mVp-p] V2 [mVp-p] 500 V2 [mVp-p] 9. Measure the delay time of the OUT pin output with respect to the input signal. When taking this measurement, exclude the delay associated with the low-pass filter.
|Some Part number from the same manufacture Sanyo Semiconductor Corporation|
|LC89960 NTSC 1H Delay Line|
|LC89962 NTSC Format Delay Line|
|LC89970 Pal CCD Delay Line|
|LC89971 Multi-system CCD Delay Line|
|LC89972M Pal CCD Delay Line|
|LC89975M Pal-format Delay Line|
|LC89977M CCD Delay Line For Pal|
|LC89978M CCD Delay Line For Multi-system|
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