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Details, datasheet, quote on part number:M374S0823ETS-C1L
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| Part: | M374S0823ETS-C1L |
| Category: | Memory => DRAM => SDR SDRAM => Modules => Unbuffered DIMM |
| Description: | Description = M374S0823ETS 8Mx72 Sdram Dimm With Ecc Based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 64 ;; Organization = 8Mx72 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 4K/64ms ;; Speed = 7C,7A,1H,1L ;; #of Pin = 168 ;; Power = C,l ;; Component Composition = (8Mx8)x9+EEPROM ;; Production Status = Eol ;; Comments = PC133&PC100 |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download M374S0823ETS-C1L datasheet File size : 171 kB |
| Request For quote: | Find where to buy M374S0823ETS-C1L
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Datasheet text preview:
M374S0823ETS
M374S0823ETS SDRAM DIMM
PC133/PC100 Unbuffered DIMM
8Mx72 SDRAM DIMM with ECC based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung M374S0823ETS is a 8M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung M374S0823ETS consists of nine CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. One 0.1uF and one 0.33 uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M374S0823ETS is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
· Performance range Part No. M374S0823ETS-C7A M374S0823ETS-C75 M374S0823ETS-C1H M374S0823ETS-C1L · · · · · Max Freq. (Speed) 133MHz (7.5ns@ CL=3) 133MHz (7.5ns @ CL=3) 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3)
Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) · All inputs are sampled at the positive going edge of the system clock · Serial presence detect with EEPROM · PCB : Height (1,375mil) , single sided component
PIN CONFIGURATIONS (Front side/back side)
P i n Front P i n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 V SS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 V SS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 V SS NC NC VDD WE DQM0 Front P i n Front P i n Back Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 *CS1 RAS V SS A1 A3 A5 A7 A9 BA0 A11 V DD *CLK1 *A12 V SS CKE0 *CS3 DQM6 DQM7 *A13 V DD NC NC CB6 CB7 V SS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VDD DQ52 NC *VR E F NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS *CLK3 NC **SA0 **SA1 **SA2 VDD 29 D Q M 1 CS0 30 31 DU 32 V SS 33 A0 34 A2 35 A4 36 A6 37 A8 38 A 1 0 / A P 39 BA1 40 VDD 41 VDD 42 C L K 0 43 V SS 44 DU 45 CS2 46 D Q M 2 47 D Q M 3 48 DU 49 VDD 50 NC 51 NC 52 CB2 53 CB3 54 V SS 55 D Q 1 6 56 D Q 1 7 57 D Q 1 8 85 V SS 58 D Q 1 9 86 D Q 3 2 59 87 D Q 3 3 VDD 60 D Q 2 0 88 D Q 3 4 61 89 D Q 3 5 NC 6 2 *VR E F 9 0 VDD 63 * C K E 1 91 D Q 3 6 64 92 D Q 3 7 VSS 65 D Q 2 1 93 D Q 3 8 66 D Q 2 2 94 D Q 3 9 67 D Q 2 3 95 D Q 4 0 68 96 V SS VSS 69 D Q 2 4 97 D Q 4 1 70 D Q 2 5 98 D Q 4 2 71 D Q 2 6 99 D Q 4 3 72 D Q 2 7 1 0 0 D Q 4 4 73 VDD 101 DQ45 74 DQ28 102 VDD 75 D Q 2 9 1 0 3 D Q 4 6 76 D Q 3 0 1 0 4 D Q 4 7 77 DQ31 105 CB4 78 VSS 106 CB5 79 C L K 2 1 0 7 V S S 80 NC 108 NC 81 NC 109 NC 82 **SDA 110 VDD 8 3 * * S C L 1 1 1 CAS 84 VDD 112 DQM4
PIN NAMES
Pin Name A0 ~ A11 BA0 ~ BA1 DQ0 ~ DQ63 CB0 ~ CB7 CLK0, CLK2 CKE0 CS0, CS2 RAS CAS WE DQM0 ~ 7 VDD VSS *VR E F SDA SCL SA0 ~ 2 DU NC Function Address input (Multiplexed) Select bank Data input/output Check bit (Data-in/data-out) Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Serial data I/O Serial clock Address in EEPROM Dont use No connection
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.2 Sept. 2001
M374S0823ETS
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select
PC133/PC100 Unbuffered DIMM
Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Check bits for ECC. Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM0 ~ 7 DQ0 ~ 63 CB0 ~ 7 VDD/VSS
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Check bit Power supply/ground
Rev. 0.2 Sept. 2001
M374S0823ETS
FUNCTIONAL BLOCK DIAGRAM
CS0 DQM0
PC133/PC100 Unbuffered DIMM
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DQM4
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U0 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U5
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U1 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM6
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U6
DQM
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CS2 DQM2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U2
DQM
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U7
· DQM CS
U3
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQM
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U8
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U4
Serial PD SCL 47K WP A0 SDA A1 A2
SA0 SA1 SA2
A0 ~ An, BA0 & 1 RAS CAS WE CKE0 10 DQn VDD Vss · · · ·
SDRAM U0 ~ U8 SDRAM U0 ~ U8 SDRAM U0 ~ U8 SDRAM U0 ~ U8 SDRAM U0 ~ U8 3 . 3 pF*1 CLK0/2 10 ·
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U0/U3 U5/U7 U1/U4
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U6/U8 U2
Every DQpin of SDRAM CLK1/3 One 0.1uF and one 0.33 uF Cap. To all SDRAMs per each SDRAM
*1 : For 4 loads, CLK2 only. 10 10p F
Rev. 0.2 Sept. 2001
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