|
Details, datasheet, quote on part number:M372F0805DT0-C
| |
| Part: | M372F0805DT0-C |
| Category: | Memory => DRAM => Async DRAM => Modules => Buffered DIMM |
| Description: | Description = M372F0805DT0 8M X 72 DRAM Dimm With Ecc Using 4Mx16 & 4Mx4, 4K Refresh, 3.3V ;; Density(MB) = 64 ;; Organization = 8Mx72 ;; Mode = Fast Page ;; Refresh = 8K/64ms ;; Speed(ns) = 50,60 ;; #of Pin = 168 ;; Component Composition = (4Mx16)x8+(4Mx4)x4 ;; Production Status = Eol ;; Comments = Buffered |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download M372F0805DT0-C datasheet File size : 494 kB |
| Request For quote: | Find where to buy M372F0805DT0-C
|
| |
Datasheet text preview:
DRAM MODULE
M372F0805DT0-C
M372F0805DT0-C EDO Mode 8M x 72 DRAM DIMM with ECC Using 4Mx16 & 4Mx4, 4K Refresh, 3.3V
GENERAL DESCRIPTION
The Samsung M372F0805DT0-C is a 8Mx72bits Dynamic RAM high density memory module. The Samsung M372F0805DT0-C consists of eight 4Mx16bits & four 4Mx4bits CMOS DRAMs in TSOP-II 400mil packages and two 16 bits driver IC in TSSOP package mounted on a 168-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The M372F0805DT0-C is a Dual In-line Memory Module and is intended for mounting into 168 pin edge connector sockets.
FEATURES
· Part Identification - M372F0805DT0-C(4096cycles/64ms Ref. TSOP ll) · Extended Data Out Mode Operation · CAS-before-RAS Refresh capability · RAS-only and Hidden refresh capability · TTL compatible inputs and outputs · Single 3.3V±0.3V power supply · JEDEC standard pinout & Buffered PDpin · Buffered input except RAS and DQ · PCB : Height(1000mil), double sided component
PERFORMANCE RANGE
Speed -C50 -C60
tR A C
50ns 60ns
tC A C
18ns 20ns
tR C
84ns 104ns
tH P C
20ns 25ns
PIN CONFIGURATIONS
Pin F r o n t P i n F r o n t Pin F r o n t P i n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 V SS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 V SS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 V SS RSVD RSVD VCC W0 CAS0 2 9 *CAS2 3 0 RAS0 31 OE0 32 V SS 33 A0 34 A2 35 A4 36 A6 37 A8 38 A10 39 A12 40 VCC 4 1 RFU 4 2 RFU 43 V SS 44 OE2 4 5 RAS2 4 6 CAS4 4 7 *CAS6 48 W2 49 VCC 50 RSVD 51 RSVD 5 2 DQ18 5 3 DQ19 54 V SS 5 5 DQ20 5 6 DQ21 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ22 DQ23 VCC DQ24 RFU RFU RFU RFU DQ25 DQ26 DQ27 V SS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 V SS PD1 PD3 PD5 PD7 ID0 VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back V SS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 V SS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 DQ53 V SS RSVD RSVD VCC RFU CAS1 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back *CAS3 RAS1 RFU V SS A1 A3 A5 A7 A9 A11 *A13 VCC RFU B0 V SS RFU RAS3 CAS5 *CAS7 PDE VCC RSVD RSVD DQ54 DQ55 V SS DQ56 DQ57 P i n Back 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ58 DQ59 VCC DQ60 RFU RFU RFU RFU DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 PD6 PD8 ID1 VCC
PIN NAMES
Pin Names A0, B0, A1 - A11 DQ0 - DQ71 W0, W2 OE0, OE2 RAS0 - RAS3 CAS0, 1,4,5 VCC V SS NC PDE PD1 - 8 ID0 - 1 RSVD RFU Function Address Input(4K ref.) Data In/Out Read/Write Enable Output Enable Row Address Strobe Column Address Strobe Power(+3.3V) Ground No Connection Presence Detect Enable Presence Detect ID bit Reserved Use Reserved for Future Use
Pins marked * are not used in this module.
PD & ID Table
Pin PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 50NS 0 0 1 1 1 0 0 0 0 60NS 0 0 1 1 1 1 1 0 0 0
ID1 0 PD Note :PD & ID Terminals must each be pulled up through a register to VCC at the next higher level assembly. PDs will be either open (NC) or driven to VSS via on-board buffer circuits. PD : 0 for Vol of Drive IC & 1 for N.C ID Note : IDs will be either open (NC) or connected directly to VSS without a buffer. ID : 0 for Vss & 1 for N.C
REV. 0.1 Oct. 2000
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
RAS1 RAS0 CAS0 W0 OE0 A0 A1-A11 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
U0
M372F0805DT0-C
CAS1
CAS5
DQ0-DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
U6 U9
DQ36-DQ51 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ52-DQ55 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ56-DQ71 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
U8 U11
RAS3 RAS2 CAS4 W2 OE2 B0 A1-A11 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
U3
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16-DQ19 DQ0 DQ1 DQ2 DQ3 DQ20-DQ35 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
U2
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
U1
U7
U10
DQ0 DQ1 DQ2 DQ3
U4
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
U5
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
Vcc 0.1 or 0.22uF Capacitor under each DRAM Vss To all DRAMs
A0 B0 A1-A11 W0, OE0 W2, OE2
U0-U2,U6-U8 U3-U5,U9-U11 U0-U11 U0-U2,U6-U8 U3-U5,U9-U11
REV. 0.1 Oct. 2000
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC T stg PD IO S Rating -0.5 to +4.6 -0.5 to +4.6 -55 to +125 12 50
M372F0805DT0-C
Unit V V °C W mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC V SS VIH V IL Min 3.0 0 2.0 -0.3* 2 Typ 3.3 0 Max 3.6 0 V C C +0.3*1 0.8 Unit V V V V
*1 : VCC+1.3V at pulse width15ns, which is measured at VCC. *2 : -1.3V at pulse width15ns, which is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
M372F0805DT0 Symbol IC C 1 IC C 2 IC C 3 IC C 4 IC C 5 IC C 6 II ( L ) IO ( L ) VOH VOL Speed -50 -60 Dont care -50 -60 -50 -60 Dont care -50 -60 Dont care Dont care Min
-
Max 666 606 100 666 606 526 466 30 666 606 10 10 0.4
Unit mA mA mA mA mA mA mA mA mA mA uA uA V V
-10 -10 2.4 -
ICC1* : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4* : Extended Data Out Mode Current * (RAS=VIL, CAS cycling : tHPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) I(IL) : Input Leakage Current (Any input 0VINVcc+0.3V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0VVOUTVcc) VOH : Output High Voltage Level (IOH = -2mA) VOL : Output Low Voltage Level (IOL = 2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC.
REV. 0.1 Oct. 2000
|
|
