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Details, datasheet, quote on part number:M368L3313CT1-CB3
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| Part: | M368L3313CT1-CB3 |
| Category: | Memory => DRAM => DDR SDRAM => Modules => Unbuffered DIMM |
| Description: | Description = M368L3313CT1 32Mx64 DDR Sdram 184pin Dimm Based on 16Mx8 ;; Density(MB) = 256 ;; Organization = 32Mx64 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 4K/64ms ;; Speed = A2,B0,A0 ;; #of Pin = 184 ;; Power = C,l ;; Component Composition = (16Mx8)x16 ;; Production Status = Eol ;; Comments = - |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download M368L3313CT1-CB3 datasheet File size : 88 kB |
| Request For quote: | Find where to buy M368L3313CT1-CB3
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Datasheet text preview:
M368L3313CT1
184pin Unbuffered DDR SDRAM MODULE
256MB DDR SDRAM MODULE
(32Mx64(16Mx64*2 bank) based on 16Mx8 DDR SDRAM)
Unbuffered 184pin DIMM 64-bit Non-ECC/Parity
Revision 0.4 May. 2002
R e v . 0.4 May.2002
M368L3313CT1
Revision History
Revision 0.0 (Mar. 2001)
1 . First release
184pin Unbuffered DDR SDRAM MODULE
Revision 0.1 (June. 2001)
1. Changed module current speificaton 2. Changed typo size on module PCB in package dimesions. (from 2.6mm to 3mm). 3. Changed AC parameter table.
Revision 0.2 (Nov. 2001)
1 . Added DDR333 function 2 . Updated DDR333 test specification 3 . Deleted typical current in IDD spec. table 4 . Included address and control input setup/hold time(tIS/tIH) at slow slew rate in DDR200/266 AC specification 5 . Deleted Exit self refresh to write command(tXSW) in DDR200/266 AC specification 6 . Changed unit of tMRD from tCK to ns at DDR333 7 . Rename tXSA(exit self refresh to bank active command) to tXSNR(exit self refresh to non read command) at DDR200/266 8 . Rename tXSR(exit self refresh to read command) to tXSRD at DDR200/266 9 . Rename tWPREH(DQS in hold time) to tWPRE at DDR200/266 1 0 . Rename tREF(Refresh interval time) to tREFI at DDR200/266
Revision 0.3 (Jan. 2002)
1 . Added tRAP(Active to Read with auto precharge command)
Revision 0.4 (May. 2002)
1 . C h a n g e pin location of A13 from pin 103 to pin 167
R e v . 0.4 May.2002
M368L3313CT1
184pin Unbuffered DDR SDRAM MODULE
M368L3313CT1 DDR SDRAM 184pin DIMM
32Mx64 DDR SDRAM 184pin DIMM based on 16Mx8 GENERAL DESCRIPTION FEATURE
T h e Samsung M368L3313CT1 is 32M bit x 64 Double Data R a t e SDRAM high density memory module. The Samsung M 3 6 8 - L3313CT1 consists of sixteen CMOS 16M x 8 bit with 4 b a n k s Double Data Rate SDRAMs in 66pin TSOP-II(400mil) p a c k a g e s mounted on a 184pin glass-epoxy substrate. Four 0 . 1 u F decoupling capacitors are mounted on the printed circuit b o a r d in parallel for each DDR SDRAM. The M368L3313CT1 D u a l In-line Memory Module and is intended for mounting into 1 8 4 p i n edge connector sockets. Synchronous design allows precise cycle control with the use o f system clock. I/O transactions are possible on every clock c y c l e . Range of operating frequencies, programmable latencies a n d burst lengths allows the same device to be useful for a varie t y of high bandwidth, high performance memory system applications. · P e r f o r m a n c e range Part No. M368L3313CT1-CB3 M368L3313CT1-CA2 M368L3313CT1-CB0 M a x Freq. 166Mhz(6ns@CL=2.5) 133MHz(7.5ns@CL=2) 133MHz(7.5ns@CL=2.5) SSTL_2 Interface
· Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
· Double-data-rate architecture; two data transfers per clock cycle
· Bidirectional data strobe(DQS) · Differential clock inputs(CK and CK) · DLL aligns DQ and DQS transition with CK transition · Programmable Read latency 2, 2.5 (clock) · Programmable Burst length (2, 4, 8) · Programmable Burst type (sequential & interleave) · Edge aligned data output, center aligned data input · Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh) · Serial presence detect with EEPROM · PCB :Height 1250 mil, double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin F r o n t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin Front Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD */CS2 DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 *A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Back VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 *CB4 *CB5 VDDQ CK0 /CK0 VSS *DM8 A10 *CB6 VDDQ *CB7 KEY VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 Pin Back 32 A5 3 3 DQ24 34 VSS 3 5 DQ25 3 6 DQS3 37 A4 3 8 VDD 3 9 DQ26 4 0 DQ27 41 A2 42 VSS 43 A1 4 4 *CB0 4 5 *CB1 4 6 VDD 4 7 *DQS8 48 A0 4 9 *CB2 50 VSS 5 1 *CB3 52 BA1 KEY 5 3 DQ32 5 4 VDDQ 5 5 DQ33 5 6 DQS4 5 7 DQ34 58 VSS 59 BA0 6 0 DQ35 6 1 DQ40 154 /RAS 155 DQ45 156 VDDQ 157 /CS0 158 /CS1 159 DM5 160 VSS 161 DQ46 162 DQ47 163 */CS3 164 VDDQ 165 DQ52 166 DQ53 167 *A13 168 VDD 169 DM6 170 DQ54 171 DQ55 172 VDDQ 173 NC 174 DQ60 175 DQ61 176 VSS 177 DM7 178 DQ62 179 DQ63 180 VDDQ 181 SA0 182 SA1 183 SA2 1 8 4 VDDSPD
PIN DESCRIPTION
P i n Name A 0 ~ A11 B A 0 ~ BA1 D Q 0 ~ DQ63 D Q S 0 ~ DQS7 CKE0,CKE1 / C S 0 , /CS1 RAS CAS WE DM0 ~ 7 VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 VDDID Function A d d r e s s input (Multiplexed) B a n k Select Address Data input/output Data Strobe input/output Clock enable input Chip select input R o w address strobe Column address strobe Write enable D a t a - in mask P o w e r supply (2.5V) P o w e r Supply for DQS(2.5V) Ground P o w e r supply for reference Serial EEPROM Power Supply ( 2.3V to 3.6V ) Serial data I/O Serial clock Address in EEPROM V D D identification flag
CK0, CK0 ~ CK2, CK2 Clock input
NC N o connection * These pins are not used in this module.
S A M S U N G ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
R e v . 0.4 May.2002
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