Details, datasheet, quote on part number: TDA8263HN/C1
PartTDA8263HN/C1
CategoryMultimedia => Set-Top Box
DescriptionFully integrated satellite tuner
The direct conversion QPSK demodulator is the front-end receiver dedicated to digital TV broadcasting, satisfying both DVB-S and DBS TV standards. The wide range oscillator (from 950 MHz to 2175 MHz) covers the American, European and Asian satellite bands, as well as the SMA-TV US standard.

The Zero-IF (ZIF) concept discards traditional IF filtering and intermediate conversion techniques.

Gain-controlled amplifiers in the RF guarantee optimum signal level. The variable gain is controlled by the signal returned from the Satellite Demodulator and Decoder (SDD) and applied to pin AGC.

The integrated LNA allows the IC to be directly connected to the LNB output. The LNA can be by-passed by an I˛C-bus selectable attenuation, providing a 20 dB extra attenuation in order to handle higher input signal levels of up to 0 dBm per channel.

Connected at the RF input, an RMS level detector provides through I˛C-bus read mode the full band input signal level.

The LO quadrature outputs are derived from a high performance integrated LC oscillator.

Its frequency is:(flo)/ = (f xtal)/R . Thanks to the low phase noise performance of the integrated LC oscillator which controls the LO frequency, the synthesizer offers a good performance for phase noise in the satellite band. The step size of the LO output frequency is equal to the comparison frequency.

Control data is entered via the I˛C-bus. The bus can be either 5.0 V or 3.3 V, allowing compatibility with most of existing microcontrollers.

An 8-byte frame is required to address the device and to program the main divider ratio, the reference divider ratio, the charge-pump current and the operating mode.

A flag is set when the loop is in-lock, readable during read operations, as well as the Power-on reset flag and RF input level.

The device has four selectable I˛C-bus addresses. Applying a specific voltage to pin AS selects an address. This feature gives the possibility to use up to four TDA8263HN ICs in the same system.


Features
Direct conversion QPSK and 8PSK demodulation (ZIF)
3.3 V DC supply voltage (no 30 V required)
950 MHz to 2175 MHz frequency range
High range input level;
-70 dBm to -15 dBm at 75 Ohm (normal mode)
Up to 0 dBm (20 dB attenuation configuration).
Low noise RF input (integrated LNA)
0 dB to 55 dB continuous variable gain on RF input
RF input level detector
Switchable 0 dB to 9 dB additional gain on baseband output amplifier
High AGC linearity (< 0.7 dB/step when used with an 8-bit DAC), AGC controlled voltage between 0.3 V and 3 V
Programmable 5 MHz to 36 MHz 5th-order baseband filters for I and Q paths
Fully integrated PLL frequency synthesizer
Low phase noise fully integrated oscillator
Operation from a 16 MHz crystal or external clock
5 frequency steps from 125 kHz to 2 MHz
Crystal frequency output to drive the demodulator IC
Compatible with 5 V and 3.3 V I˛C-bus
Fully compatible and easy to interface with the PS digital satellite demodulators family
32-pin low thermal resistance package.


Applications
Direct Broadcasting Satellite (DBS) QPSK demodulation
Digital Video Broadcasting (DVB) QPSK demodulation
BS digital 8PSK demodulation
DVB-S2 8PSK demodulation.
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload TDA8263HN/C1 datasheet
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PackagesSOT617-1 (HVQFN32)
  

 

Features, Applications

The direct conversion QPSK demodulator is the front-end receiver dedicated to digital TV broadcasting, satisfying both DVB-S and DBS TV standards. The wide range oscillator (from 950 MHz to 2175 MHz) covers the American, European and Asian satellite bands, as well as the SMA-TV US standard. The Zero-IF (ZIF) concept discards traditional IF filtering and intermediate conversion techniques. Gain-controlled amplifiers in the RF guarantee optimum signal level. The variable gain is controlled by the signal returned from the Satellite Demodulator and Decoder (SDD) and applied to pin AGC. The integrated LNA allows the to be directly connected to the LNB output. The LNA can be by-passed an I2C-bus selectable attenuation, providing 20 dB extra attenuation in order to handle higher input signal levels to 0 dBm per channel. Connected at the RF input, an RMS level detector provides through I2C-bus read mode the full band input signal level. The LO quadrature outputs are derived from a high performance integrated LC oscillator. LO f XTAL Its frequency is: = Thanks to the low phase noise performance of the N R integrated LC oscillator which controls the LO frequency, the synthesizer offers a good performance for phase noise in the satellite band. The step size of the LO output frequency is equal to the comparison frequency. Control data is entered via the I2C-bus. The bus can be either 3.3 V, allowing compatibility with most of existing microcontrollers. An 8-byte frame is required to address the device and to program the main divider ratio, the reference divider ratio, the charge-pump current and the operating mode. A flag is set when the loop is in-lock, readable during read operations, as well as the Power-on reset flag and RF input level. The device has four selectable I2C-bus addresses. Applying a specific voltage to pin AS selects an address. This feature gives the possibility to use up to four TDA8263HN ICs in the same system.

Direct conversion QPSK and 8PSK demodulation (ZIF) V DC supply voltage (no 30 V required) 950 MHz to 2175 MHz frequency range High range input level; x -70 dBm to -15 dBm at 75 (normal mode) to 0 dBm (20 dB attenuation configuration). Low noise RF input (integrated LNA) 55 dB continuous variable gain on RF input RF input level detector Switchable 9 dB additional gain on baseband output amplifier High AGC linearity 0.7 dB/step when used with an 8-bit DAC), AGC controlled voltage between 0.3 V and 3 V Programmable 5 MHz to 36 MHz 5th-order baseband filters for I and Q paths Fully integrated PLL frequency synthesizer Low phase noise fully integrated oscillator Operation from a 16 MHz crystal or external clock 5 frequency steps from 125 kHz to 2 MHz Crystal frequency output to drive the demodulator IC Compatible with 5 V and V I2C-bus Fully compatible and easy to interface with the PS digital satellite demodulators family 32-pin low thermal resistance package.

Direct Broadcasting Satellite (DBS) QPSK demodulation Digital Video Broadcasting (DVB) QPSK demodulation BS digital 8PSK demodulation DVB-S2 8PSK demodulation.

Table 1: Symbol VCC ICC fosc Vo(I/Q)(rms) Quick reference data Parameter supply voltage supply current oscillator frequency absolute quadrature error recommended I and Q output voltage RMS value (QPSK signals) LPF cut-off frequency 5-bit controlled measured at 10 MHz

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

oscillator phase noise in 100 kHz offset; the satellite band fcomp = 1 MHz synthesizer noise floor in 1 kHz and10 kHz the satellite band offset; fcomp = 1 MHz amplifier gain control range ambient temperature

The product is qualified with an output voltage 550 mV (p-p) differential, however larger values can be used at baseband outputs that might have impact on the product performance. Phase noise in optimal conditions, see related application note.

Noise figure at maximum gain: 8 dB High linearity:
Low synthesizer noise floor: -78 dBc/Hz at 1 kHz and 10 kHz offset with

AGC linearity: < 0.7 dB/step with a 8-bit DAC Maximum I/Q amplitude mismatch: 1 dB Maximum I/Q quadrature mismatch: 5° Symbol rates: from 1 MBd to 45 MBd.

Table 2: Ordering information Package Name TDA8263HN HVQFN32 Description plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body mm Version SOT617-1 Type number


 

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