|Category||Multimedia => Video => TV Applications => TV Tuner|
|Description||TDA8261TW; Satellite Zero-if QPSK/8PSK Downconverter With PLL Synthesizer;; Package: SOT549-1 (HTSSOP32)|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download TDA8261TW datasheet
FEATURES Direct conversion Quadrature Phase Shift Keying (QPSK) and 8PSK demodulation (Zero-IF) to 2175 MHz frequency range High-level asymmetrical RF input 50 dB variable gain on RF input Loop-controlled to 90° phase shifter High AGC linearity (<1 dB per bit with an 8-bit DAC), AGC between 0 and 3 V External baseband filters for In-phase (I) and Quadrature (Q) signal paths I2C-bus controlled PLL frequency synthesizer Low phase noise Operation from a 4 MHz crystal (allowing the use of an SMD crystal) Five frequency steps from 125 kHz to 2 MHz Crystal frequency output to drive demodulator IC Compatible with 5, 3.3 and V I2C-bus Fully compatible and easy to interface with digital satellite demodulators of the Philips Semiconductors family V DC supply voltage 32-pin high heat-dissipation package. APPLICATIONS Direct Broadcasting Satellite (DBS) QPSK demodulation Digital Video Broadcasting (DVB) QPSK demodulation BS digital 8PSK demodulation. GENERAL DESCRIPTION The direct conversion QPSK demodulator is the front-end receiver dedicated to digital TV broadcasting, satisfying both DVB and DBS TV standards. The wide range oscillator (from to 2175 MHz) covers the American, European and Asian satellite bands, as well as the Satellite Master Antennae (SMA) TV US standard. The Zero-IF concept discards traditional IF filtering and intermediate conversion techniques. It also simplifies the signal path.
Optimum signal level is guaranteed by gain controlled amplifiers in the RF path. The 50 dB variable gain is controlled by the signal returned from the Satellite Demodulator and Decoder (SDD) and applied to pin AGCIN. The PLL synthesizer is built on a dual-loop concept. The first loop controls a fully integrated L-band oscillator, using the LC VCO as a reference which runs at a quarter of the synthesized frequency. The second loop controls the tuning voltage of the VCO and improves the phase noise of the carrier within the loop bandwidth. The step size is equal to the comparison frequency. The input of the main divider of the PLL synthesizer is connected internally to the VCO output. The comparison frequency of the second loop is obtained from an oscillator driven by an external 4 MHz crystal. The 4 MHz output available at pin XTOUT may be used to drive the crystal inputs of the SDD, saving an additional crystal in the application. Both the divided and the comparison frequencies of the second loop are compared in a fast phase detector which drives the charge pump. The TDA8261TW includes a loop amplifier with an internal high-voltage transistor to drive an external 33 V tuning voltage. Control data is entered via the I2C-bus. The I2C-bus voltage can 2.5 V, allowing compatibility with most of the existing microcontrollers. A 5-byte frame is required to address the device and to program the main divider ratio, the reference divider ratio, the charge pump current and the operating mode. A flag is set when the loop is `in-lock'. This flag can be read during read operations, as well as the Power-On Reset (POR) flag. The device has four selectable I2C-bus addresses. The selection is done by applying a specific voltage to pin AS. This feature gives the possibility to use up to four TDA8261TW ICs in the same system.
Performance summary TDA8261TW performance: Noise figure at maximum gain = +18 dB High linearity; = +19 dBm and = +14 dBm Low phase noise on baseband outputs: -78 dBc/Hz (foffset = 1 and 10 kHz; fCOMP = 1 MHz) 50 dB variable gain with AGC control AGC linearity <1 dB/bit with an 8-bit DAC Maximum I-to-Q amplitude mismatch 1 dB QUICK REFERENCE DATA SYMBOL VCC ICC Vo(p-p) fosc n PARAMETER supply voltage supply current output voltage (peak-to-peak value) quadrature error oscillator frequency phase noise on baseband outputs CONDITIONS foffset = 1 and 10 kHz; - fCOMP = 1 MHz with appropriate loop filter and charge pump MIN. 4.75 TYP.
Maximum I-to-Q phase mismatch = 3° Signal rates from to 45 Msymbol/s (depending on the external filter). System performance, for example, in a tuner application with the TDA8261TW placed after a low-cost discrete LNA: Noise figure at maximum gain = 8 dB High linearity; = 15 dBm and = 5 dBm 50 dB variable gain with AGC control.
dynamic range of voltage gain from pins RFA or RFB to 48 pins IBBOUT or QBBOUT crystal oscillator output voltage on pin XTOUT (peak-to-peak value) ambient temperature = 0; driving a load = 10 pF; M 400
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8261TW HTSSOP32 DESCRIPTION plastic, heatsink thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm VERSION SOT549-1
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