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Details, datasheet, quote on part number:PCF8549U/2
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
PCF8549 65 × 102 pixels matrix LCD driver
Product specification File under Integrated Circuits, IC12 1997 Nov 21
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
FEATURES · Single chip LCD controller/driver · 65 row and 102 column outputs · Display data RAM 65 × 102 bits · On-chip: Generation of LCD supply voltage Generation of intermediate LCD bias voltages Oscillator requires no external components (external clock also possible) · 400 kHz Fast I2C Interface · CMOS compatible inputs · Mux rate: 65 · Logic supply voltage range VDD1 - VSS: 1.5 to 6 V · Voltage generator voltage range VDD2/2_HV - VSS: 2.4 to 5 V · Display supply voltage range VLCD - VSS: 7.0 to 16 V · Low power consumption, suitable for battery operated systems · Temperature compensation of VLCD · Interlacing for better display quality · Slim chip layout, suited for chip-on-glass applications. APPLICATIONS · Telecom equipment · Portable instruments · Point of sale terminals. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8549U/2/F1 TRAY chip with bumps in tray DESCRIPTION GENERAL DESCRIPTION
PCF8549
The PCF8549 is a low power CMOS LCD controller driver, designed to drive a graphic display of 65 rows and 102 columns. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The PCF8549 interfaces to most microcontrollers via an I2C interface. Packages The PCF8549U/2 is available as bumped die. Sawn wafer as chip sorted in chip tray. For further details see Section "Bonding pads". Customized TCP upon request.
VERSION
1997 Nov 21
2
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
BLOCK DIAGRAM
PCF8549
C0 to C101
R0 to R64
COLUMN DRIVERS
ROW DRIVERS
DATA LATCHES VLCD2 Bias voltage generator
SHIFT REGISTER
OSCILLATOR VLCD1 HVGEN 7 stages Dual Ported RAM 65x102 Bit TIMING GENERATOR
OSC
IIC INTERFACE
DISPLAY CONTROL LOGIC
Fig.1 Block diagram.
1997 Nov 21
3
VDD1 VDD2 VDD2_HV VSS1 VSS2 VSS2_HV
SDA_out SDA SCL
RES
SA0
T1 T2 T3 T4 T5
T6 T7
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