|
|
Part: 74HCT112DB
Category:
Logic
-> Flip-Flops
Description: 74HC112;74HCT112; Dual JK Flip-flop With Set And Reset; Negative-edge Trigger;; Package: SOT338-1 (SSOP16)
Company: Philips Semiconductors
Datasheet: Download 74HCT112DB datasheet File size : 201 kB
Request For quote: Find where to buy 74HCT112DB
Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT112 Dual JK flip-flop with set and reset; negative-edge trigger
Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06 1998 Jun 10
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; negative-edge trigger
FEATURES · Asynchronous set and reset · Output capability: standard · ICC category: flip-flops GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT112 are dual negative-edge triggered JK-type flip-flops featuring individual nJ, nK, clock (nCP), set (nSD) and reset (nRD) inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
74HC/HCT112
The set and reset inputs, when LOW, set or reset the outputs as shown in the function table regardless of the levels at the other inputs. A HIGH level at the clock (nCP) input enables the nJ and nK inputs and data will be accepted. The nJ and nK inputs control the state changes of the flip-flops as shown in the function table. The nJ and nK inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Output state changes are initiated by the HIGH-to-LOW transition of nCP. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V maximum clock frequency input capacitance power dissipation capacitance per flip-flop notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 17 15 18 66 3.5 27 19 15 19 70 3.5 30 ns ns ns MHz pF pF HCT UNIT
1998 Jun 10
2
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; negative-edge trigger
ORDERING INFORMATION TYPE NUMBER 74HC112D; 74HCT112D 74HC112DB; 74HCT112DB 74HC112N; 74HCT112N 74HC112PW; 74HCT112PW PACKAGE NAME SO16 SSOP16 DIP16 TSSOP16 DESCRIPTION plastic small outline package; 16 leads; body width 3.9 mm
74HC/HCT112
VERSION SOT109-1 SOT338-1 SOT38-1 SOT403-1
plastic shrink small outline package; 16 leads; body width 5.3 mm plastic dual in-line package; 16 leads (300 mil); long body plastic thin shrink small outline package; 16 leads; body width 4.4 mm
PIN DESCRIPTION PIN NO. 1, 13 2, 12 3, 11 4, 10 5, 9 6, 7 8 15, 14 16 SYMBOL 1CP, 2CP 1K, 2K 1J, 2J 1SD, 2SD 1Q, 2Q 1Q, 2Q GND 1RD, 2RD VCC NAME AND FUNCTION clock input (HIGH-to-LOW, edge triggered) data inputs; flip-flops 1 and 2 data inputs; flip-flops 1 and 2 set inputs (active LOW) true flip-flop outputs complement flip-flop outputs ground (0 V) reset inputs (active LOW) positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jun 10
3
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; negative-edge trigger
FUNCTION TABLE INPUTS OPERATING MODE nSD asynchronous set asynchronous reset undetermined toggle load "0" (reset) load "1" (set) hold "no change" Note L H L H H H H nRD H L L H H H H nCP X X X nJ X X X h l h l
74HC/HCT112
OUTPUTS nK X X X h h l l nQ H L H q L H q nQ L H L q H L q
Fig.4 Functional diagram.
1. If nSD and nRD simultaneously go from LOW to HIGH, the output states will be unpredictable. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP transition X = don't care = HIGH-to-LOW CP transition
Fig.5 Logic diagram (one flip-flop).
1998 Jun 10
4
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; negative-edge trigger
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: flip-flops
74HC/HCT112
1998 Jun 10
5
Others parts begin by 74
74-1 74-2 74-3 74-4 74-5 74-6 74-7 74-8 74-9 74-10 74-11 74-12 74-13 74-14 74-15 74-16 74-17 74-18 74-19 74-20 74-21 74-22 74-23 74-24 74-25 74-26 74-27 74-28 74-29 74-30 74-31 74-32 74-33 74-34 74-35 74-36 74-37 74-38 74-39 74-40 74-41 74-42 74-43 74-44 74-45 74-46 74-47 74-48 74-49 74-50 74-51 74-52 74-53 74-54 74-55 74-56 74-57 74-58 74-59 74-60 74-61 74-62
|
|
|
