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Part: 74HCT10N
Category:
Description: 74HC/HCT10; Triple 3-input NAND Gate;; Package: SOT27-1 (DIP14)
Company: Philips Semiconductors
Datasheet: Download 74HCT10N datasheet File size : 201 kB
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT10 Triple 3-input NAND gate
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Triple 3-input NAND gate
FEATURES · Output capability: standard · ICC category: SSI GENERAL DESCRIPTION
74HC/HCT10
The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + (CL × VCC2 × fO) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V (CL × VCC2 × fo) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V. ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay nA, nB, nC to nY input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 9 3.5 12 11 3.5 14 HCT ns pF pF UNIT
December 1990
2
Philips Semiconductors
Product specification
Triple 3-input NAND gate
PIN DESCRIPTION PIN NO. 1, 3, 9 2, 4, 10 13, 5, 11 12, 6, 8 7 14 SYMBOL 1A to 3A 1B to 3B 1C to 3C 1Y to 3Y GND VCC NAME AND FUNCTION data inputs data inputs data inputs data outputs ground (0 V) positive supply voltage
74HC/HCT10
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
FUNCTION TABLE INPUTS nA L L L L H H H H Notes Fig.4 Functional diagram. Fig.5 Logic diagram (one gate). 1. H = HIGH voltage level L = LOW voltage level nB L L H H L L H H nC L H L H L H L H OUTPUT nY H H H H H H H L
December 1990
3
Philips Semiconductors
Product specification
Triple 3-input NAND gate
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HC SYMBOL PARAMETER +25 min. tPHL/ tPLH propagation delay nA, nB, nC to nY typ. 30 11 9 tTHL/ tTLH output transition time 19 7 6 -40 to + 85 max. min. 95 19 16 75 15 13 max. 120 24 20 95 19 16 -40 to + 125 min. max. 145 29 25 110 22 19 ns ns UNIT
74HC/HCT10
TEST CONDITIONS VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 Fig.6 WAVEFORMS
December 1990
4
Philips Semiconductors
Product specification
Triple 3-input NAND gate
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: SSI Note to HCT types
74HC/HCT10
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT nA, nB, nC
UNIT LOAD COEFFICIENT 1.5
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HCT SYMBOL PARAMETER + 25 min. tPHL/ tPLH tTHL/ tTLH propagation delay nA, nB, nC to nY output transition time typ. 14 7 max. 24 15 -40 to + 85 min. max. 30 19 -40 to +125 min. max. 36 22 ns ns 4.5 4.5 Fig.6 Fig.6 UNIT VCC (V) WAVEFORMS TEST CONDITIONS
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the input (nA, nB, nC) to output (nY) propagation delays and the output transition times.
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1990
5
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