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Part: 74AVC16836
Category:
Interface and Interconnect
Description: 20-bit Registered Driver With Inverted Register Enable 3-state
Company: Philips Semiconductors
Datasheet: Download 74AVC16836 datasheet File size : 93 kB
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Datasheet text preview:
INTEGRATED CIRCUITS
74AVC16836 20-bit registered driver with inverted register enable (3-State)
Preliminary specification
Replaces datasheet 74AVC16836/74AVCH16836 dated 1998 Dec 07
1999 Jul 23
Philips Semiconductors
Philips Semiconductors
Preliminary specification
20-bit registered driver with inverted register enable (3-State)
74AVC16836
FEATURES
· Wide supply voltage range of 1.2 V to 3.6 V · Complies with JEDEC standard no. 8-1A/5/7. · CMOS low power consumption · Input/output tolerant up to 3.6 V · DCO (Dynamic Controlled Output) circuit dynamically changes
output impedance, resulting in noise reduction without speed degradation
PIN CONFIGURATION
OE Y0 Y1 GND Y2 Y3 VCC Y4 Y5 Y6 GND Y7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CP A0 A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 A19 LE
· Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
· Power off disables 74AVC16836 outputs, permitting Live Insertion
DESCRIPTION
The 74AVC16836 is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor (Live Insertion). A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient. See the graphs on page 8 for typical curves.
Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 VCC Y16 Y17 GND Y18 Y19 NC
SH00159
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.0 ns; CL = 30 pF. PARAMETER SYMBOL tPHL/tPLH Propagation delay An to Yn Propagation delay LE to Yn; CP to Yn Input capacitance Power dissipation capacitance per buffer dissi ca er buffer VI = GND to VCC1 GND to Outputs enabled Output disabled VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V CONDITIONS TYPICAL 2.6 2.0 1.7 3.0 2.4 2.0 5.0 25 6 UNIT ns
tPHL/tPLH CI CP D
ns pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES 56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II TEMPERATURE RANGE 40°C to +85°C ORDER CODE 74AVC16836 DGG DRAWING NUMBER SOT364-1
1999 Jul 23
2
Philips Semiconductors
Preliminary specification
20-bit registered driver with inverted register enable (3-State)
74AVC16836
PIN DESCRIPTION
PIN NUMBER 28 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 4, 11, 18, 25, 32, 35, 39, 46, 53 7, 22, 35, 50 1 29 56 55, 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 SYMBOL NC Y0 to Y19 NAME AND FUNCTION No connection Data outputs
LOGIC SYMBOL (IEEE/IEC)
OE CP LE 1 56 29 C3 G2 EN1 2C3
GND VCC OE LE CP
Ground (0V) Positive supply voltage Output enable input (active LOW) Latch enable input (active LOW) Clock input
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 27 1 1 3D
55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
A0 to A19
Data inputs
Y9 Y10 Y11 Y12 Y13 Y14 Y15
LOGIC SYMBOL
OE
Y16 Y17
CP
Y18 Y19
LE
A0
SH00160
D LE CP Y0
FUNCTION TABLE
INPUTS OE H L L L L L L H L X Z = = = = = LE X L L H H H H CP X X X H L A X L H L H X X OUTPUTS Z L H L H Y01 Y02
TO THE 19 OTHER CHANNELS
SH00163
HIGH voltage level LOW voltage level Don't care High impedance "off" state LOW-to-HIGH level transition
NOTES: 1. Output level before the indicated steady-state input conditions were established, provided that CP is high before LE goes low. 2. Output level before the indicated steady-state input conditions were established.
1999 Jul 23
3
Philips Semiconductors
Preliminary specification
20-bit registered driver with inverted register enable (3-State)
74AVC16836
168-pin SDR SDRAM DIMM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM
BACK SIDE
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
FRONT SIDE AVC16836 AVC16836 AVC16836 PCK2509S or PCK2510S
The PLL clock distribution device and AVC registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER DC supply voltage (according to JEDEC Low Voltage Standards) VCC DC supply voltage (for low voltage applications) VI VO Tamb tr, tf DC Input voltage range DC output voltage range; output 3-State DC output voltage range; output HIGH or LOW state Operating free-air temperature range Input rise and fall times VCC = 1.65 to 2.3 V VCC = 2.3 to 3.0 V VCC = 3.0 to 3.6 V CONDITIONS MIN 1.65 2.3 3.0 1.2 0 0 0 40 0 0 0 MAX 1.95 2.7 3.6 3.6 3.6 3.6 V VCC +85 30 20 10 °C ns/V V UNIT
SDRAM
SW00409
V
1999 Jul 23
4
Philips Semiconductors
Preliminary specification
20-bit registered driver with inverted register enable (3-State)
74AVC16836
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0 V) SYMBOL PARAMETER VCC IIK VI IOK VO VO IO IGND, ICC Tstg PTOT DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output 3-State DC output voltage; output HIGH or LOW state DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package plastic thin-medium-shrink (TSSOP) For temperature range: 40 to +125 °C above +55°C derate linearly with 8 mW/K VI t0 For all inputs1 VO uVCC or VO t 0 Note 1 Note 1 VO = 0 to VCC CONDITIONS RATING 0.5 to +4.6 50 0.5 to 4.6 "50 0.5 to 4.6 0.5 to VCC +0.5 "50 "100 65 to +150 600 UNIT V mA V mA V V mA mA °C mW
NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER VCC = 1.2 V VIH HIGH level Input voltage level In voltage VCC = 1.65 to 1.95 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 1.2 V VIL LOW level Input voltage level In voltage VCC = 1.65 to 1.95 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 1.65 to 3.6 V; VI = VIH or VIL; IO = 100 µA VOH HIGH level output voltage VCC = 1.65 V; VI = VIH or VIL; IO = 4 mA VCC = 2.3 V; VI = VIH or VIL; IO = 8 mA VCC = 3.0 V; VI = VIH or VIL; IO = 12 mA VCC = 1.65 to 3.6 V; VI = VIH or VIL; IO = 100 µA VOL LOW level output voltage VCC = 1.65 V; VI = VIH or VIL; IO = 4 mA VCC = 2.3 V; VI = VIH or VIL; IO = 8 mA VCC = 3.0 V; VI = VIH or VIL; IO = 12 mA II IOFF IIHZ/IILZ IOZ Input leakage current g 3-State output OFF-state current 3-State output OFF-state current VCC = 1.65 to 3.6 V; 1 65 to 3 6 VI = VCC or GND or GND VCC = 0 V; VI or VO = 3.6 V VCC = 1.65 to 3.6 V; VI = VCC or GND VCC = 1.65 to 2.7 V; VI = VIH or VIL; VO = VCC or GND VCC = 3.0 to 3.6 V; VI = VIH or VIL; VO = VCC or GND VCC = 1.65 to 2.7 V; VI = VCC or GND; IO = 0 VCC = 3.0 to 3.6 V; VI = VCC or GND; IO = 0 TEST CONDITIONS Temp = -40°C to +85°C MIN VCC 0.65VCC 1.7 2.0 VCC*0.20 VCC*0.45 VCC*0.55 VCC*0.70 TYP1 0.9 1.2 1.5 0.9 1.2 1.5 VCC VCC*0.10 VCC*0.28 VCC*0.32 GND 0.10 0.26 0.36 0.1 0.1 0.1 0.1 0.1 0.1 0.2 MAX GND 0.35VCC 0.7 0.8 0.20 0.45 0.55 0.70 2.5 "10 12.5 5 µA 10 20 40 µA µA µA µA V V V V UNIT
out OFF-state current 3-State output OFF-state current
ICC
Quiescent supply current su current
NOTES: 1. All typical values are at Tamb = 25°C. 1999 Jul 23 5
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