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Part: 74ABT16374B
Category:
Logic
-> Flip-Flops
Description: 74ABT16374B; 74ABTH16374B; 16-bit D-type Flip-flop; Positive-edge Trigger (3-State);; Package: SOT370-1 (SSOP48)
Company: Philips Semiconductors
Datasheet: Download 74ABT16374B datasheet File size : 294 kB
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INTEGRATED CIRCUITS
74ABT16374B 74ABTH16374B 16-bit D-type flip-flop; positive-edge trigger (3-State)
Product specification Supersedes data of 1995 Sep 28 IC23 Data Handbook 1998 Feb 27
Philips Semiconductors
Philips Semiconductors
Product specification
16-bit D-type flip-flop; positive-edge trigger (3-State)
74ABT16374B 74ABTH16374B
FEATURES
· Two 8-bit positive edge triggered registers · Live insertion/extraction permitted · Power-up 3-State · Power-up reset · Multiple VCC and GND pins minimize switching noise · 3-State output buffers · 74ABTH16373B incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused inputs
DESCRIPTION
The 74ABT16374B high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16374B has two 8-bit, edge triggered registers, with each register coupled to eight 3-State output buffers. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. Each active-Low Output Enable (nOE) controls all eight 3-State buffers for its register independent of the clock operation. When nOE is Low, the stored data appears at the outputs for that register. When nOE is High, the outputs for that register are in the High-impedance "OFF" state, which means they will neither drive nor load the bus. Two options are available, 74ABT16374B which does not have the bus-hold feature and 74ABTH16374B which incorporates the bus-hold feature. CONDITIONS Tamb = 25°C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC VO = 0V or VCC; 3-State Outputs disabled; VCC = 5.5V Outputs Low; VCC = 5.5V OUTSIDE NORTH AMERICA 74ABT16374B DL 74ABT16374B DGG 74ABTH16374B DL 74ABTH16374B DGG NORTH AMERICA BT16374B DL BT16374B DGG BH16374B DL BH16374B DGG
· Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
· Output capability: +64mA/32mA · Latch-up protection exceeds 500mA per JEDEC Std 17 · ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ ICCL Propagation delay nCP to nQx Input capacitance Output capacitance Quiescent supply current su current PARAMETER TYPICAL 2.6 2.2 4 7 500 8 UNIT ns pF pF µA mA
ORDERING INFORMATION
PACKAGES 48-Pin Plastic SSOP Type III 48-Pin Plastic TSSOP Type II 48-Pin Plastic SSOP Type III 48-Pin Plastic TSSOP Type II TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C DWG NUMBER SOT370-1 SOT362-1 SOT370-1 SOT362-1
PIN DESCRIPTION
PIN NUMBER 47, 46, 44, 43, 41, 40, 38, 37 36, 35, 33, 32, 30, 29, 27, 26 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 19, 20, 22, 23 1, 24 48, 25 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 SYMBOL 1D0 1D7 2D0 2D7 1Q0 1Q7 2Q0 2Q7 1OE, 2OE 1CP, 2CP GND VCC FUNCTION
LOGIC SYMBOL
47 46 44 43 41 40 38 37
Data inputs
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
Data outputs Output enable inputs (active-Low) Clock pulse inputs (active rising edge) Ground (0V) Positive supply voltage
48 1
1CP 1OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
2 36
3 35
5 33
6 32
8 30
9 29
11 27
12 26
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7 25 24 2CP 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
13
14
16
17
19
20
22
23
SH00078
1998 Feb 27
2
853-1752 19027
Philips Semiconductors
Product specification
16-bit D-type flip-flop; positive-edge trigger (3-State)
74ABT16374B 74ABTH16374B
LOGIC SYMBOL (IEEE/IEC)
1OE 1CP 2OE 2CP 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1 48 24 25 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 2D 2 1EN C1 2EN C2 1D 1 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
PIN CONFIGURATION
1OE 1Q0 1Q1 GND 1Q2 1Q3 V CC 1Q4 1Q5 GND 1Q6 1Q7 2Q0 2Q1 GND 2Q2 2Q3 V CC 2Q4 2Q5 GND 2Q6 2Q7 2OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1CP 1D0 1D1 GND 1D2 1D3 V CC 1D4 1D5 GND 1D6 1D7 2D0 2D1 GND 2D2 2D3 V CC 2D4 2D5 GND 2D6 2D7 2CP
SH00077
SA00326
LOGIC DIAGRAM
nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7
D
D
D
D
D
D
D
D
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
nCP
nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7
SA00327
1998 Feb 27
3
Philips Semiconductors
Product specification
16-bit D-type flip-flop; positive-edge trigger (3-State)
74ABT16374B 74ABTH16374B
FUNCTION TABLE
INPUTS nOE L L L H H H= h= L= l= NC = X= Z= = = nCP nDx l h X X nDx INTERNAL REGISTER L H NC NC nDx OUTPUTS OPERATING MODE MODE nQ0 nQ7 L H NC Z Z Load and read register Hold Disable outputs
High voltage level High voltage level one set-up time prior to the High-to-Low E transition Low voltage level Low voltage level one set-up time prior to the High-to-Low E transition No change Don't care High impedance "off" state Low-to-High clock transition Not a Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 DC output diode current DC output voltage3 VO < 0 output in Off or High state output in Low state DC output current output current output in High state Storage temperature range 64 65 to 150 °C VI < 0 CONDITIONS RATING 0.5 to +7.0 18 1.2 to +7.0 50 0.5 to +5.5 128 mA UNIT V mA V mA V
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level Input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 40 PARAMETER MIN 4.5 0 2.0 0.8 32 64 10 +85 MAX 5.5 VCC UNIT V V V V mA mA ns/V °C
1998 Feb 27
4
Philips Semiconductors
Product specification
16-bit D-type flip-flop; positive-edge trigger (3-State)
74ABT16374B 74ABTH16374B
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C MIN VIK VOH VOL VRST II Input clamp voltage VCC = 4.5V; IIK = 18mA VCC = 4.5V; IOH = 3mA; VI = VIL or VIH High-level output voltage VCC = 5.0V; IOH = 3mA; VI = VIL or VIH VCC = 4.5V; IOH = 32mA; VI = VIL or VIH Low-level output voltage Power-up output voltage3 Input leakage current leakage current 74ABT16374B VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5 5V; VI = VCC or GND 5.5V; or GND VCC = 5.5V; VI = VCC or GND VCC = 5.5V; VI = VCC VCC = 5.5V; VI = 0 IHOLD IOFF IPU/PD IOZH IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 74ABT16374B Additional supply current per input pin2 74ABTH16374B Quiescent supply current Bus H ld current i Hold t inputs6 t 74ABTH16374B Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output current1 VCC = 4.5V; VI = 0.8V VCC = 4.5V; VI = 2.0V VCC = 5.5V; VI = 0 to 5.5V VCC = 0.0V; VO or VI 4.5V VCC = 2.1V; VO = 0.5V; VI = GND or VCC; V OE = GND VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 50 Control pins Data pins5 pins 50 75 ±800 ±5.0 ±5.0 0.5 0.5 5.0 70 0.5 8 0.5 ±100 ±50 10 10 50 180 2 19 2 50 ±100 ±50 10 10 50 180 2 19 2 µA µA µA µA µA mA mA mA mA µA 2.5 3.0 2.0 TYP 0.9 2.9 3.4 2.4 0.42 0.13 0.01 ±0.01 0.01 1 0.55 0.55 ±1 ±1 1 3 50 75 µA MAX 1.2 2.5 3.0 2.0 0.55 0.55 ±1 ±1 1 5 µA V V µA V Tamb = 40°C to +85°C MIN MAX 1.2 V UNIT
II
Input leakage current leakage current 74ABTH16374B
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC
5
100
100
ICC
0.5
1.5
1.5
mA
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a transition time of up to 100µsec is permitted. 5. Unused pins at VCC or GND. 6. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 27
5
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