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Details, datasheet, quote on part number:PI7C7100C-33
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Datasheet text preview:
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PI7C7100
3 Port PCI-to-PCI Bridge
Datasheet Brief
Product Features
All three ports compliant with the PCI Local Bus Specification, Revision 2.1 Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.0 32-Bit Primary and two Secondary Ports Circular-Delta Bus Architecture Concurrent primary to secondary bus operation and independent intra-secondary port channel to reduce traffic on the primary port Provides arbitration for two sets of 8 secondary bus masters Programmable 2-level priority arbiters Disable control for use of external arbiter Support PCI transactions for: All I/O and memory commands Type 1 to Type 0 configuration conversion (downstream only) Type 1 to Type 1 configuration forwarding Type 1 to special cycle configuration conversion Supports posted memory write buffers in all directions Implements delayed transactions for all PCI configuration, I/O and memory read commands Supports positive medium decoding Enhanced address decoding 32-Bit I/O address range 32-Bit memory-mapped I/O address range VGA addressing and VGA palette snooping ISA-aware mode for legacy support in the first 64KB of I/O address range IEEE 1149.1 JTAG interface support Full scan support 3.3V core logic with 5V tolerant 3.3V PCI signaling interface 256-pin plastic PBGA package (NA256) Supports system transaction ordering rules Hot-Plug "Ready"
Product Description
Pericoms PI7C7100 is the first triple port PCI-to-PCI Bridge device designed to be fully compliant with the 32-Bit, 33 MHz implementation of the PCI Local Bus Specification, Revision 2.1. The PI7C7100 supports synchronous bus transactions between devices on the primary bus and the secondary buses both operating at 33 MHz. The primary and the secondary buses can also operate in concurrent mode, resulting in additional increase in system performance. Concurrent bus operation offloads and isolates unnecessary traffic from the primary bus; thereby enabling a master and a target device on the same secondary PCI bus to communicate even while the primary bus is busy.
Product Benefits
Triple port PCI-to-PCI Bridge increases the number of PCI slots that can be supported in a system. Single PI7C7100 device instead of two PCI-to-PCI Bridge devices conserves board real estate and provides one less device load on the primary bus. Concurrent and intra-secondary bus communication increases overall system performance by reducing bus traffic on the primary bus. Devices on secondary busses can independently communicate while the primary bus is busy. Integrated two-level programmable arbiter support for up to 8 devices on each secondary bus maximizes master device control. The internal arbiter can be bypassed with an external arbiter for custom applications. Synchronous clock operation on the primary and secondary busses Enhanced PCI bridge performance and efficiency through support for delayed transactions.
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PI7C7100 3 Port PCI-to-PCI Bridge
Primar y Arbiter REQ/GNT Transaction Queue & Buffers
PRIMARY INTERFACE
Transaction Queue & Data Buffers 1 Arbiter REQ/GNT 1 (Qty. 8)
Configuration Registers A/B
Clock (Qty. 16) PRIMARY AND SECONDARY CONTROL PRIMARY MASTER/ TARGET INTERFACE
Transaction Queue & Data Buffers 2 Arbiter REQ/GNT 2 (Qty. 8)
SECONDARY INTERFACE 2
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MASTER/ TARGET INTERFACE 2
SECONDARY INTERFACE 1
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Datasheet Brief
PI7C7100 Block Diagram
MASTER/ TARGET INTERFACE 1
2
06/01/00
PI7C7100 3 Port PCI-to-PCI Bridge PI7C7100 Pin Information
P_AD [31:0] P_CBE [3:0] P_PAR P_FRAME# P_IRDY# P_TRDY# P_DEVSEL# P_STOP# P_LOCK# P_IDSEL P_PERR# P_SERR# P_REQ# P_GNT# PRIMARY BUS INTERFACE SECONDARY 1 BUS INTERFACE S1_AD[31:0] S1_CBE [3:0] S1_PAR S1_FRAME# S1_IRDY# S1_TRDY# S1_DEVSEL# S1_STOP# S1_LOCK# S1_IDSEL S1_PERR# S1_SERR# S1_REQ# [7:0] S1_GNT# [7:0] S1_RESET# S1_EN P_RESET# P_M66EN P_CLK P_FLUSH# CONTROL INPUT CLOCK CONTROL
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Datasheet Brief
S_CLKOUT [15:0] S_CFN# S_M66EN
S2_AD [31:0] S2_CBE [3:0] S2_PAR TCK TMS TDO TDI TRST# JTAG INTERFACE SECONDARY 2 BUS INTERFACE FULL TEST SCAN S2_FRAME# S2_IRDY# S2_TRDY# S2_DEVSEL# S2_STOP# S2_LOCK# S2_IDSEL S2_PERR# S2_SERR# S2_REQ# [7:0] S2_GNT# [7:0] S2_RESET# S2_EN
SCANEN
3
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06/01/00
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