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Details, datasheet, quote on part number:PI74LVTC245S
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Datasheet text preview:
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PI74LVTC245
3.3V 8-Bit Bi-Directional Transceiver with 3-State Outputs
Product Features
· Advanced low power CMOS design for 2.7V to 3.6V VCC operation · Supports 5V input/output tolerance in mixed signal mode operation · Function compatible with LVT family of products · Balanced ±24mA output drive · Typical VOLP (Output Ground Bounce) <0.8V at VCC=3.3V, TA=25°C · Ioff and Power Up/Down 3-State support live insertion · Latch-up performance exceeds 200mA Per JESD78 · ESD protection exceeds JESD 22 - 2000V Human-Body Model (A114-B) - 200V Machine Model (A115-A) · Packages (Pb-free available): - 20-pin 209-mil wide plastic SSOP (H) - 20-pin 173-mil wide plastic TSSOP (L) 20-pin 300-mil wide plastic SOIC (S)
Product Description
Pericom Semiconductor's PI74LVTC series of logic circuits are produced using the Company's advanced CMOS technology, achieving industry leading speed. The PI74LVTC245 is a non-inverting 8-bit Bidirectional Transceiver designed for low-voltage 2.7V to 3.6V VCC operation, with the capability of interfacing to the 5V system environment. This tranceiver is designed for asynchronous two-way communication between data buses. The direction control input pin (DIR) determines the d i r e c t i o n of the dataflow from the A bus to the B bus or from the B bus to the A bus. The output enable (OE) input, when HIGH, disables both A and B ports by placing them in HIGH Z condition. When Vcc is between 0 to 1.5V during power up or power down, the outputs of the device are in the high-impedance state. To ensure the high-impedance state above 1.5V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. The device fully supports live-insertion with its Ioff and power-up/ down 3-state. The Ioff circuitry disables the outputs when the power is off, preventing the backflow of damaging current through the device. Power-up/down 3-state places the outputs in the high-impedance state during power up or power down, preventing driver conflict.
Logic Block Diagram
DIR OE A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7
Product Pin Configuration
DIR A0 A1 A2 A3 A4 A5 A6 A7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 VCC OE B0 B1 B2 B3 B4 B5 B6 B7
20-Pin 16 H, L, S 15
14 13 12 11
1
PS8691
07/01/03
Truth Table(4)
Inputs OE L L H
Notes: 4. H = High Signal Level L = Low Signal Level X = Don't Care or Irrelevant Z = High Impedance
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC245 3.3V, 8-Bit Bi-Directional Tranceiver with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC ....... 0.5V to +6.5V Input voltage range, VI(1) ......... 0.5V to +6.5V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ........ 0.5V to +6.5V Voltage range applied to any output in the active state, VO(1),(2) ......... 0.5V to VCC +0.5V Input clamp current, IIK (VI <0) .... 50mA Output clamp current, IOK (VO <0) ....... 50mA Continous Output Current IO ...... ±50mA Continous Current through each VCC or GND pin ...... ±100mA Package thermal impedance, JA(3):package H ... 81°C/W package L .... 84°C/W package S .... 84°C/W Storage Temperature range, Tstg ............ 65°C to 150°C
Notes: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. Input negative-voltage and output voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 6.5 maximum 3. The package thermal impedance is calculated in accordance with JESD 51.
Product Pin Description
Pin Name OE DIR xAx xBx GND VCC De s cription 3- State Output Enable Inputs (Active LOW) Direction Control Input Side A Inputs or 3- State Outputs Side B Inputs or 3- State Outputs Ground Power
Outputs DIR L H X Bus B Data to Bus A Bus A Data to Bus B Z
2
PS8691
07/01/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC245 3.3V, 8-Bit Bi-Directional Tranceiver with 3-State Outputs
Recommended Operating Conditions(5)
M in. VC C VIH VIL VI VO Supply Voltage High- level Input Voltage Low- level Input Voltage Input Voltage Output Voltage High or Low State 3- State VC C = 2.7V VC C = 3.0V to 3.6V VC C = 2.7V VC C = 3.0V to 3.6V Operating VC C = 2.7V to 3.6V VC C = 2.7V to 3.6V 0 0 0 2.7 2.0 0.8 5.5 VC C 5.5 12 24 12 24 6 150 40 85 ns/V µs/V °C mA V M a x. 3.6 Units
IO H High- level output current IO L Low- level output current t/V Input transition rise or fall rate t/VC C Power- up ramp rate TA Operating free- air temperature
Notes: 5. All unused inputs must be held at VCC or GND to ensure proper device operation.
3
PS8691
07/01/03
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