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Details, datasheet, quote on part number:PI74FCT16823TV
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Datasheet text preview:
Product Features:
Common Features: · PI74FCT16823T and PI74FCT162823T are high-speed, low power devices with high current drive. · VCC = 5V ±10% · Hysteresis on all inputs · Packages available: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 300 mil wide palstic SSOP (V) PI74FCT16823T Features: · High output drive: IOH = 32 mA; IOL = 64 mA · Power off disable outputs permit "live insertion" · Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C PI74FCT162823T Features: · Balanced output drivers: ±24 mA · Reduced system switching noise · Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA = 25°C PI74FCT162H823T Features: · Bus Hold retains last active bus state during 3-state · Eliminates the need for external pull-up resistors
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PI74FCT16823T/162823/162H823T PI74FCT16823T 18-BIT REGISTERS
PI74FCT162823T PI74FCT162H823T
Fast CMOS 18-Bit Registers
Product Description:
Pericom Semiconductor's PI74FCT series of logic circuits are produced in the Company's advanced 0.6 micron CMOS technology, achieving industry leading speed grades. The PI74FCT16823T, PI74FCT162823T and PI74FCT162H823 are 18-bit wide registers with clock enable (xCLKEN) and clear (xCLR) controls that make these devices especially suitable for parity bus interfacing in high-performance systems. The devices can be operated as two 9-bit registers or one 18-bit register using the control inputs. Signal pins are arranged in a flow-through organization for ease of layout and hysteresis is designed into all inputs to improve noise margin. The PI74FCT16823T output buffers are designed with a PowerOff disable function allowing "live insertion" of boards when the devices are used as backplane drives. The PI74FCT162823T has ±24 mA balanced output drivers. It is designed with current limiting resistors at its outputs to control the output edge rate resulting in lower ground bounce and undershoot. This eliminates the need for external terminating resistors for most interface applications. The PI74FCT162H823T has "Bus Hold" which retains the input's last state whenever the input goes to high-impedance preventing "floating" inputs and eliminating the need for pull-up/down resistors.
Logic Block Diagram
1O E 1C L R 1C L K 1C L K E N
2OE 2CLR 2CLK 2CLKEN
R C D
1D 1 1 Q1
R C D
2D1 2Q1
To 8 other channels
To 8 other channels
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PS2040A 03/11/96
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PI74FCT16823T/162823/162H823T 18-BIT REGISTERS
Product Pin Configuration
1CLR 1OE 1Q1 GND 1Q2 1Q3
Product Pin Description
56 55 54 53 52 51 50 49 48 47 46
1CLK 1CLKEN 1D1 GND 1D2 1D3
1 2 3 4 5 6 7 8 9 10 11
VCC
1Q4 1Q5 1Q6
VCC
1D4 1D5 1D6
Pin Name Description xDx Data Inputs(1) xCLK Clock Inputs xCLKEN Clock Enable Inputs (Active LOW) xCLR Asynchronous Clear Inputs (Active LOW) xOE Output Enable Inputs (Active LOW) xQx 3-State Outputs Note: 1. For the PI74FCT162H823T, these pins have "Bus Hold." All other pins are standard, outputs, or I/Os.
GND
1Q7 1Q8 1Q9 2Q1 2Q2 2Q3
GND
1D7 1D8 1D9 2D1 2D2 2D3 GND 2D4 2D5 2D6 VCC 2D7 2D8
12 56-PIN 45 V56 44 13 A56 14 43 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29
PI74FCT16823 Truth Table(1)
Inputs Outputs
GND
2Q4 2Q5 2Q6
VCC
2Q7 2Q8
Function xOE High-Z H Clear L Hold L Load H H L L 1.
xCLR xCLKEN xCLK X X X L X X H H X H L H L H L H L
xDx X X X L H L H
xQx Z L Q(2) Z Z L H
GND
2Q9 2OE 2CLR
GND 2D9
2CLKEN 2CLK
2.
H = High Voltage Level L = Low Voltage Level X = Don't Care Z = High Impedance NC = No Change = LOW-to-HIGH Transition Output level before indicated steady-state input conditions were established.
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PS2040A 03/11/96
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PI74FCT16823T/162823/162H823T 18-BIT REGISTERS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ........... 65°C to +150°C Ambient Temperature with Power Applied ... 40°C to +85°C Supply Voltage to Ground Potential (Inputs & Vcc Only) ..... 0.5V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) .. 0.5V to +7.0V DC Input Voltage .......... 0.5V to +7.0V DC Output Current .... 120 mA Power Dissipation ......... 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = 40°C to +85°C, VCC = 5.0V ± 10%)
Parameters Description VIH VIL II H II H II H II H IIL IIL IIL IIL IBHH I BHL IOZH(5) IOZL(5) VIK IO S IO VH Input HIGH Voltage Input LOW Voltage Input HIGH Current Input HIGH Current Input HIGH Current Input HIGH Current Input LOW Current Input LOW Current Input LOW Current Input LOW Current Bus Hold Sustain Current High-Impedance Output Current (3-STATE OUTPUTS) Clamp Diode Voltage Short Circuit Current Output Drive Current Input Hysteresis Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level Standard Input, VCC = Max. Standard I/O, VCC = Max. Bus Hold Input(4), VCC = Max. Bus Hold I/O(4), VCC = Max. Standard Input, VCC = Min. Standard I/O, VCC = Min. Bus Hold Input(4), VCC = Min. Bus Hold I/O(4), VCC = Min. Bus Hold Input(4), VCC = Min. VCC = Max. VCC = Max. VCC = Min., IIN = 18 mA VCC = Max.(3), VOUT = GND VCC = Max.(3), VOUT = 2.5V Min. 2.0 VIN = VCC VIN = VCC VIN = VCC VIN = VCC VIN = GND VIN = GND VIN = GND VIN = GND VIN = 2.0V VIN = 0.8V VOUT = 2.7V VOUT = 0.5V 0.8 1 1 ±100 ±100 1 1 ±100 ±100 50 +50 1 1 0.7 140 100 1.2 200 180 Typ(2) Max. Units V V µA µA µA µA µA µA µA µA µA µA µA V mA mA mV
80 50
Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Pins with Bus Hold are identified in the pin description. 5. This specification does not apply to bi-directional functionalities with Bus Hold.
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PS2040A 03/11/96
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