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Details, datasheet, quote on part number:PI74ALVCH16270
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Datasheet text preview:
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16270 PI74ALVCH16270 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs 12-Bit
PI74ALVCH16270
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs
Product Description
Product Features
· · · · · · · · PI74ALVCH16270 is designed for low voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C Bus Hold retains last active bus state during 3-STATE, eliminating the need for external pullup resistors Industrial operation at 40°C to +85°C Packages available: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 300 mil wide plastic SSOP (V)
Pericom Semiconductor's PI74ALVCH series of logic circuits are produced in the Company's advanced 0.5 micron CMOS technology, achieving industry leading speed. The PI7ALVCH16270 is used in applications where data must be transferred from a narrow high-speed bus to a wider lower frequency bus. The device provides synchronous data exchange between the two p o r t s . Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate CLKEN inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two stage pipeline is provided in the A-to1B path,with a single storage register in the A-to-2B path. Proper control of the CLKENA inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). The control terminals are registered to synchronize the bus direction changes with the CLK. To ensure the high-impedance state during power up or power down, OE should be tied to Vcc through a pullup resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Logic Block Diagram
1
PS8171A
03/05/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16270 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs 12-Bit Registered Truth Tables(1)
Inputs CLK OEA H H L L OEB H L H L A Z Z Active Active Outputs 1B, 2B Z Active Z Active
Product Pin Description
Pin Name OE CLK SEL CLKEN A,1B,2B GND VCC Description Output Enable Input (Active LOW) Clock Select (Active Low) Clock Enable (Active Low) 3-State Outputs Ground Power
A to B Storage (OEB = L)
Product Pin Configuration
OEB CLKENA2 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 CLKENA1 CLK
INPUTS CLKENA1 CLKENA2 CLK A X X L H L H X
OUTPUTS 1B 1B0(3) 1B0(3) L(2 ) H(2 ) 1B0(3 ) 1B0(3 ) 1B0(3 ) 2B 2B0(3 ) 2B0(3 ) L H L H 2B0(3 )
OEA CLKEN1B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 CLKEN2B SEL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52
L L L L H H H
H H L L L L H
X X X
56-PIN 51 A56 50 V56
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
B to A Storage (OEA = L)
Inputs CLK EN 1B H X L L X X CLK EN2B CLK X H X X L L X X SEL H L H H L L 1B X X L H X X 2B X X X X L H Outputs A A0( 3 ) A0( 3 ) L H L H
Notes: 1. H = High Signal Level L = Low Signal Level X = Irrelevant Z = High Impedance = Transition, Low to High 2. Two CLK edges are needed to propagate data. 3. Output level before the indicated steady state input conditions were established.
2
PS8171A
03/05/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16270 PI74ALVCH16270 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs 12-Bit
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ... 65°C to +150°C Ambient Temperature with Power Applied .. 40°C to +85°C Input Voltage Range, VIN .... 0.5V to VCC +0.5V Output Voltage Range, VOUT ............ 0.5V to VCC +0.5V DC Input Voltage .......... 0.5V to +5.0V DC Output Current ...... 100 mA Power Dissipation .. 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = 40°C to +85°C, VCC = 3.3V ± 10%) DC
Parame te rs VCC VIH(3) VIL(3) VIN(3) VO UT(3) D e s cription Supply Voltage Input HIGH Voltage VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V 0 0 IOH = -100mA, VCC = Min. to Max. Output HIGH Voltage VIH = 1.7V, IO H = -6mA, VCC = 2.3V VIH = 1.7V, IOH = -12mA, VCC = 2.3V VIH = 2.0V, IOH = -12mA, VCC = 2.7V VIH = 2.0V, IOH = -12mA, VCC = 3.0V VIH = 2.0V, IOH = -24mA, VCC = 3.0V IOL = 100mA, VIL = Min. to Max. Output LOW Voltage VIL = 0.7V, IOL = 6mA, VCC = 2.3V VIL = 0.7V, IO L = 12mA, VCC = 2.3V VIL = 0.8V, IO L = 12mA, VCC = 2.7V VIL = 0.8V, IO L = 24mA, VCC = 3.0V Output HIGH C urrent VCC = 2.3V VCC = 2.7V VCC = 3.0V Output LOW C urrent VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC -0.2 2.0 1.7 2.2 2.4 2.0 0. 2 0. 4 0. 7 0. 4 0.55 - 12 - 12 - 24 mA 12 12 24 V Te s t Conditions (1) M in. 2.3 1.7 2.0 0. 7 0. 8 VCC VCC Typ.(2) M ax. 3. 6 Units
Input LOW Voltage Input Voltage Output Voltage
VOH
VO L
IOH(3)
IOL(3)
3
PS8171A
03/05/03
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