Details, datasheet, quote on part number: PE42672
PartPE42672
Category
DescriptionSP7T Ultracmos¢â 2.75 V Switch 100 - 3000 MHz, +68 dBM IIP3
CompanyPeregrine Semiconductor Corp.
DatasheetDownload PE42672 datasheet
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Features, Applications

Features

and TX3 ports for GSM/EDGE Three pin CMOS logic control with integral decoder/driver Exceptional harmonic performance: = -84 dBc and = -77 dBc Low TX insertion loss: at 900 MHz, at 1900 MHz ­ RX Isolation at 900 MHz, at 1900 MHz 1500 V HBM ESD tolerance all ports +68 dBm IIP3 -111 dBm IMD3 No blocking capacitors required

Figure 2. Die Top View* The is a HaRPTM-enhanced SP7T RF Switch developed on the UltraCMOSTM process technology. It addresses the specific design needs of the Quad-Band GSM Handset Antenna Switch Module Market for use in GSM/EDGE/PCS/DCS/WCDMA handsets. The switch is comprised of three TX ports and four RX ports. TX1 is designed for WCDMA and TX2 and TX3 are designed for GSM/ EDGE. The four symmetric RX ports can be used for GSM/EDGE/PCS RX. On-chip CMOS decoder logic facilitates three-pin low voltage CMOS control, while high ESD tolerance V at all ports, no blocking capacitor requirements, and on-chip SAW filter overvoltage protection devices make this the ultimate in integration and ruggedness. Peregrine's HaRPTM technology enhancements deliver high linearity and exceptional harmonics performance. is an innovative feature of the UltraCMOSTM process, providing performance superior to GaAs with the economy and integration of conventional CMOS.

©2005 Peregrine Semiconductor Corp. All rights reserved. Page of 4
Document No. 70-0197-01 www.psemi.com Contact sales@psemi.com for full version of datasheet

/ 900 MHz, +35 dBm output power, / 1900 MHz, +33 dBm output power, / 900 MHz, +35 dBm output power, / 1900 MHz, +33 dBm output power, 50

Note: 1. Insertion loss specified with optimal impedance matching.

Parameter Temperature range VDD Supply Voltage IDD Power Supply Current (VDD V) TX input power2 (VSWR 3:1) RX input power (VSWR =1:1)

Min Typ Max Units PIN(50 ) dBm V VESD ESD Voltage at ANT Port (IEC 1700 V Symbol VDD VI TST Parameter/Conditions Power supply voltage Voltage on any input Storage temperature range TX input power ) RX input power (50 )

PIN (:1) TX input power (VSWR = :1) ESD Voltage (HBM, MIL_STD 883 Method 3015.7)
Note: 2. Assumes RF input period 4620 µs and duty cycle of 50%.

Note: 3. Assumes RF input period 4620 µs and duty cycle V DD within operating range specified in Table 2.

Part performance is not guaranteed under these conditions. Exposure to absolute maximum conditions for extended periods of time may adversely affect reliability. Stresses in excess of absolute maximum ratings may cause permanent damage.

©2005 Peregrine Semiconductor Corp. All rights reserved. Page of 4 Document No. 70-0197-01 UltraCMOSTM RFIC Solutions Contact sales@psemi.com for full version of datasheet

RF I/O - TX1 Ground (Requires two bond wires) RF I/O ­ TX2 Ground RF I/O ­ TX3 Ground Supply Switch control input, CMOS logic level Ground Switch control input, CMOS logic level Switch control input, CMOS logic level Ground RF I/O ­ RX4 Ground RF I/O ­ RX3 Ground RF I/O ­ RX2 Ground RF I/O ­ RX1

When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating.

Notes: 5. Bond wires should be physically short and connected to ground plane for best performance. 6. Blocking capacitors needed only when non-zero DC voltage present.

Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up.

Order Code 42672-99 42672-00 Description PE42672-DIE-400G PE42672-DIE-1H Package Film Frame Waffle Pack Evaluation Kit Shipping Method Wafer (Gross Die / Wafer Quantity) 400 Dice / Waffle Pack 1/ box

©2005 Peregrine Semiconductor Corp. All rights reserved. Page of 4

 

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