Details, datasheet, quote on part number: SN74LS253
CategoryLogic => Multiplexers/Demultiplexers => Multiplexers->Bipolar->LS Family
TitleMultiplexers->Bipolar->LS Family
DescriptionDual 4-input Multiplexer With 3-state Outputs
CompanyON Semiconductor
DatasheetDownload SN74LS253 datasheet
Cross ref.Similar parts: SN74LS151D, SN74LS151DR2, SN74LS153D, SN74LS153DR2, SN74LS157D, SN74LS157DR2, SN74LS158D, SN74LS158DR2, SN74LS251D, SN74LS251DR2
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Features, Applications

The LSTTL / MSI is a Dual 4-Input Multiplexer with 3-state outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (E0) inputs, allowing the outputs to interface directly with bus oriented systems. It is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families.

Schottky Process for High Speed Multifunction Capability Non-Inverting 3-State Outputs Input Clamp Diodes Limit High Speed Termination Effects

Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Min 4.75 0 Typ 5.0 25 Max Unit C mA

VCC Zb 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. Za 8 GND

LOADING (Note a) PIN NAMES S0, S1 Multiplexer I3a Za Multiplexer I3b Zb Common Select Inputs Output Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 U.L. 0.5 U.L. 0.5 U.L. 65 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 U.L. 0.25 U.L. 0.25 U.L. 15 U.L.

The LS253 contains two identical 4-Input Multiplexers with 3-state outputs. They select two bits from four sources selected by common select inputs (S0, S1). The 4-input multiplexers have individual Output Enable (E0a, E0b) inputs which when HIGH, forces the outputs to a high impedance (high Z) state. The LS253 is the logic implementation 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown below:

If the outputs of 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so that there is no overlap.


H = HIGH Level L = LOW Level X = Irrelevant (Z) = High Impedance (off) Address inputs S0 and S1 are common to both sections.


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0-C     D-L     M-R     S-Z