|Category||Logic => Registers|
|Description||Universal 4-Bit Shift Register, Package: Soic, Pins=16|
|Datasheet||Download SN74LS195ADR2 datasheet
|Cross ref.||Similar parts: SN74LS194AD, SN74AS194|
The is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all ON Semiconductor TTL products.
Typical Shift Right Frequency of 39 MHz Asynchronous Master Reset J, K Inputs to First Stage Fully Synchronous Serial or Parallel Data Transfers Input Clamp Diodes Limit High Speed Termination Effects
Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Min 4.75 0 Typ 5.0 25 Max Unit °C mA
Device SN74LS195AD SN74LS195ADR2 Package 16 Pin DIP SOIC16 Shipping 2000 Units/Box 38 Units/Rail 2500/Tape & Reel
VCC PE 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual InLine Package. P3 8 GND
LOADING (Note a) PIN NAMES - Q3 Parallel Enable (Active LOW) Input Parallel Data Inputs First Stage J (Active HIGH) Input First Stage K (Active LOW) Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs Complementary Last Stage Output HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. 5 U.L.
The Logic Diagram and Truth Table indicate the functional characteristics of the LS195A 4-Bit Shift Register. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The LS195A has two primary modes of operation, shift right ³ Q1) and parallel load which are controlled by the state of the Parallel Enable (PE) input. When the PE input is HIGH, serial data enters the first flip-flop Q0 via the J and K inputs and is shifted one bit in the direction ³ Q3 following each LOW to HIGH clock transition. The JK inputs provide the flexibility of the JK type input for special applications, and the simple D type input for general applications by tying the two pins together. When the PE
input is LOW, the LS195A appears as four common clocked D flip-flops. The data on the parallel inputs P3 is transferred to the respective Q2, Q3 outputs following the LOW to HIGH clock transition. Shift left operations ³ Q2) can be achieved by tying the Qn Outputs to the Pn1 inputs and holding the PE input LOW. All serial and parallel data transfers are synchronous, occurring after each LOW to HIGH clock transition. Since the LS195A utilizes edge-triggering, there is no restriction on the activity of the K, Pn and PE inputs for logic operation except for the set-up and release time requirements. A LOW on the asynchronous Master Reset (MR) input sets all Q outputs LOW, independent of any other input condition.
INPUTS OPERATING MODES Asynchronous Reset Shift, Set First Stage Shift, Reset First Shift, Toggle First Stage Shift, Retain First Stage Parallel Load q0 p1 OUTPUTS q2 p3
L = LOW voltage levels H = HIGH voltage levels X = Don't Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition. h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition. pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.
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