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Details, datasheet, quote on part number:M14440EJ1V0DS00
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Datasheet text preview:
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4483362
8M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 256K-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
Description
The µPD4483362 is a 262,144 words by 36 bits synchronous static RAM fabricated with advanced CMOS technology using Full-CMOS six-transistor memory cell. The µPD4483362 is suitable for applications which require synchronous operation, high-speed, low voltage, highdensity memory and wide bit configuration, such as cache and buffer memory. The µPD4483362 is packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for high density and low capacitive loading.
Features
· Fully synchronous operation · HSTL Input / Output levels · Fast clock access time : 3.8 ns (133 MHz) · Asynchronous output enable control : /G · Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9) · Common I/O using three-state outputs · Internally self-timed write cycle · Late write with 1 dead cycle between Read-Write · 3.3 V (Chip) / 1.5 V (I/O) supply · 100-pin PLASTIC LQFP package, 14 mm x 20 mm · Sleep Mode : ZZ (Enables sleep mode, active high)
Ordering Information
Part number Access time 3.8 ns Clock frequency 133 MHz Package 100-pin PLASTIC LQFP (14 x 20)
µPD4483362GF-A75
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Document No. M14440EJ1V0DS00 (1st edition) Date Published April 2001 NS CP(K) Printed in Japan
©
2001
µPD4483362
Pin Configuration (Marking Side)
/xxx indicates active low signal.
100-pin PLASTIC LQFP (14 x 20) [ µPD4483362GF ]
SA17 /SBd /SBb /SBa VREF /SBc SA6 SA7 SA8 SA9 /SW VDD VSS
/SS
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQc9 DQc8 DQc7 VDDQ VSSQ DQc6 DQc5 DQc4 DQc3 VSSQ VDDQ DQc2 DQc1 NC VDD NC VSS DQd1 DQd2 VDDQ VSSQ DQd3 DQd4 DQd5 DQd6 VSSQ VDDQ DQd7 DQd8 DQd9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQb9 DQb8 DQb7 VDDQ VSSQ DQb6 DQb5 DQb4 DQb3 VSSQ VDDQ DQb2 DQb1 VSS NC VDD ZZ DQa1 DQa2 VDDQ VSSQ DQa3 DQa4 DQa5 DQa6 VSSQ VDDQ DQa7 DQa8 DQa9
SA5
SA4
SA3
SA2
SA1
SA0
NC
VREF
VDD
VREF
NC
VSS
NC
SA10
SA11
SA12
SA13
NC
/G
/K
K
SA14
SA15
Remark Refer to Package Drawing for 1-pin index mark. 2
Preliminary Data Sheet M14440EJ1V0DS
SA16
µPD4483362
Pin Name and Functions
Pin name SA0 to SA17 Pin No. Description
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input 45, 46, 47, 48, 49, 50, 83
DQa1 to DQa9 DQb1 to DQb9 DQc1 to DQc9 DQd1 to DQd9 /SS /SW /SBa Note1 /SBb /SBc /SBd /G ZZ
Note2 Note1 Note1 Note1
63, 62, 59, 58, 57, 56, 53, 52, 51 68, 69, 72, 73, 74, 75, 78, 79, 80 13, 12, 9, 8, 7, 6, 3, 2, 1 18, 19, 22, 23, 24, 25, 28, 29, 30 98 85 93 95 96 97 86 64 89, 88 15, 41, 65, 91 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 38, 43, 87 14, 16, 31, 39, 42, 66, 84, 92, 94
Synchronous Data Input / Output
Synchronous Chip Select Synchronous Byte Write Enable Synchronous Byte "a" Write Enable Synchronous Byte "b" Write Enable Synchronous Byte "c" Write Enable Synchronous Byte "d" Write Enable Asynchronous Output Enable Asynchronous Sleep Mode Main Clock Input Core Power Supply Ground Output Buffer Power Supply Output Buffer Ground Input Reference No Connection
K, /K VDD VSS VDDQ VSSQ VREF NC
Notes 1. If Byte Write Operation is not used, Byte Write Pins (/SBa, /SBb, /SBc, /SBd) are to be tied to VSS. 2. If Sleep Mode is not used, ZZ Pin is to be tied to VSS.
Remark This device only supports Single Differential Clock, R / R Mode. (R / R stands for Registered Input / Registered Output.)
Preliminary Data Sheet M14440EJ1V0DS
3
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