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Details, datasheet, quote on part number:M13945EJ5V0DS00
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Datasheet text preview:
DATA SHEET
µPD23C64202L
64M-BIT SYNCHRONOUS MASK-PROGRAMMABLE ROM 4M-WORD BY 16-BIT (WORD MODE) / 2M-WORD BY 32-BIT (DOUBLE WORD MODE)
MOS INTEGRATED CIRCUIT
Description
The µPD23C64202L is a 67,108,864 bits synchronous mask-programmable ROM with multiplexed address bus. The word organization is selectable (WORD mode : 4,194,304 words by 16 bits, DOUBLE WORD mode : 2,097,152 words by 32 bits). The µPD23C64202L is packed in 86-pin PLASTIC TSOP (II).
Features
· Fully synchronous mask-ROM; all signals referenced to a positive clock edge · Word organization : 4,194,304 words by 16 bits (WORD mode) 2,097,152 words by 32 bits (DOUBLE WORD mode) · Operation frequency : up to 100 MHz
Operation supply voltage VCC Clock frequency MHz Access time from CLK ns (MAX.) Operating current (Burst mode) mA (MAX.) 150 Standby current (CMOS level input) µA (MAX.) 100
5
3.3 V ± 0.3 V
100 83 66 50 33
6 8 9 9 9
· Programmable wrap type : Sequential or Interleave · Programmable burst length : 4, 8 · Programmable /CAS latency : 3, 4, 5 or 6 · Programmable /RAS latency : 1, 2 · Burst termination by BURST STOP command · LVTTL compatible inputs and outputs
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
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Document No. M13945EJ5V0DS00 (5th edition) Date Published August 2001 NS CP (K) Printed in Japan
The mark ! shows major revised points.
©
1999
µPD23C64202L
Ordering Information
Part number Package 86-pin PLASTIC TSOP (II) (10.16 mm (400))
µPD23C64202LG5-×××-9JH
××× : ROM code suffix
Pin Configuration (Marking Side)
/xxx indicates active low signal. 86-pin PLASTIC TSOP (II) (10.16 mm (400)) [ µPD23C64202LG5-×××-9JH ]
VCC O0 VCCQ O16 O1 VSSQ O17 O2 VCCQ O18 O3 VSSQ O19 /MR VCC DQM IC /CAS /RAS /CS /WORD A12 A11 A10 A0 A1 A2 IC VCC NC O4 VSSQ O20 O5 VCCQ O21 O6 VSSQ O22 O7 VCCQ O23 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS O31 VSSQ O15 O30 VCCQ O14 O29 VSSQ O13 O28 VCCQ O12 IC VSS NC NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 IC VSS NC O27 VCCQ O11 O26 VSSQ O10 O25 VCCQ O9 O24 VSSQ O8 VSS
Remarks 1. IC : Internally connected; leave this pin unconnected or connect to GND. NC : Not internally connected; signal can be applied. 2. Refer to 13. Package Drawing for the 1-pin index mark.
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Data Sheet M13945EJ5V0DS
µPD23C64202L
Pin Name
Symbol CLK CKE /CS /RAS /CAS /MR /W ORD A0 - A12 O0 - O15, O16 - O31 Clock input Clock enable input Chip select Row address strobe Column address strobe Mode register enable Mode select (DOUBLE WORD / WORD) Address inputs Data outputs Pin name 68 67 20 19 18 14 21 25, 26, 27, 60, 61, 62, 63, 64, 65, 66, 24, 23, 22 2, 5, 8, 11, 31, 34, 37, 40, 45, 48, 51, 54, 74, 77, 80, 83, 4, 7, 10, 13, 33, 36, 39, 42, 47, 50, 53, 56, 76, 79, 82, 85 DQM VCC VCCQ VSS VSSQ NC IC DQ mask enable Supply voltage (for internal circuit) Supply voltage (for output buffer) Ground (for internal circuit) Ground (for output buffer) No connection Internal connection 16 1, 15, 29, 43 3, 9, 35, 41, 49, 55, 75, 81 44, 58, 72, 86 6, 12, 32, 38, 46, 52, 78, 84 30, 57, 69, 70, 71 17, 28, 59, 73 Pin number
Block Diagram
CLK CKE
Clock generator
Row decoder
Row buffer
Memory Cell Matrix 4,194,304 words by 16 bits (WORD mode) or 2,097,152 words by 32 bits (DOUBLE WORD mode)
A0 - A12
Mode register
Column decoder
Column buffer
Sense amplifier
Command decoder
/CS /RAS /CAS /MR /WORD
Control logic
Output control
DQM
Output buffer
O0 - O31
Data Sheet M13945EJ5V0DS
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