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Details, datasheet, quote on part number:M10060EJ7V0DSJ1
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Datasheet text preview:
DATA SHEET
MOS INTEGRATED CIRCUIT
µP D 4 8 5 5 0 6
LINE BUFFER 5K-WORD BY 16-BIT/10K-WORD BY 8-BIT
Description
The µPD485506 is a high speed FIFO (First In First Out) line buffer. Word organization can be changed either 5,048 words by 16 bits or 10,096 words by 8 bits. Its CMOS static circuitry provides high speed access and low power consumption. The µPD485506 can be used for one line delay and time axis conversion in high speed facsimile machines and digital copiers. Moreover, the µPD485506 can execute read and write operations independently on an asynchronous basis. Thus the µPD485506 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for the synchronization of multiple input signals. There are four versions, E, K, P, X and L. This data sheet can be applied to the version X and L. These versions operate with different specifications. Each version is identified with its lot number (refer to 7. Example of Stamping).
Features
· 5,048 words by 16 bits (Word mode) /10,096 words by 8 bits (Byte mode) · Asynchronous read/write operations available · Variable length delay bits; 21 to 5,048 bits or 10,096 bits (Cycle time: 25 ns) 15 to 5,048 bits or 10,096 bits (Cycle time: 35 ns) · Power supply voltage VCC = 5.0 V ±0.5 V · Suitable for sampling two lines of A3 size paper (16 dots/mm) · All input/output TTL compatible · 3-state output · Full static operation; data hold time = infinity
Ordering Information
Part Number R/W Cycle Time 25 ns 35 ns Package 44-pin plastic TSOP (II) (10.16 mm (400))
µP D 4 8 5 5 0 6 G 5 - 2 5 - 7 J F µP D 4 8 5 5 0 6 G 5 - 3 5 - 7 J F
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M10060EJ7V0DSJ1 (7th edition) Date Published December 2000 N CP(K) Printed in Japan
The mark
shows major revised points.
©
1994
µPD485506
Pin Configuration (Marking side)
44-pin plastic TSOP (II) (10.16 mm (400)) [ µP D 4 8 5 5 0 6 G 5 - 7 J F ]
DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 OE RE GND RSTR RCK VCC DOUT8 DOUT9 DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 DOUT15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 WE MD GND RSTW WCK VCC DIN8 DIN9 DIN10 DIN11 DIN12 DIN13 DIN14 DIN15
D IN0 to DIN15 WCK RCK WE RE OE RSTW RSTR MD V CC GND Remark
: Data Inputs : Write Clock Input : Read Clock Input : Write Enable Input : Read Enable Input : Output Enable Input : Reset Write Input : Reset Read Input : Mode Set Input : +5.0 V Power Supply : Ground
D OUT0 to DOUT15 : Data Outputs
Refer to Package Drawing for the 1-pin index mark.
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D a t a Sheet M10060EJ7V0DS00
µPD485506
Block Diagram
VCC GND
RSTW WCK WE
Write Address Pointer
Read Address Pointer
RSTR RCK RE
DIN0 DIN1
Output Controller Input Controller
DOUT0 DOUT1 Memory Cell Array
Output Buffer Input Buffer
DIN2 DIN3 DIN4 DIN5 DIN6 DIN7
DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7
40,384 bits (5,048 words by 8 bits)
OE
DIN8 DIN9
Input Controller
DOUT8 DOUT9 Memory Cell Array 40,384 bits (5,048 words by 8 bits)
Output Controller
DIN10 DIN11 DIN12 DIN13 DIN14 DIN15
DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 DOUT15
Mode Controller
MD
Output Buffer
Input Buffer
D a t a Sheet M10060EJ7V0DS00
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