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Details, datasheet, quote on part number:PC8477B
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| Part: | PC8477B |
| Category: | Interface and Interconnect => Floppy Disk/IDE |
| Description: | Advanced Floppy Disk Controller |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download PC8477B datasheet File size : 591 kB |
| Request For quote: | Find where to buy PC8477B
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Datasheet text preview:
PC8477B (SuperFDC) Advanced Floppy Disk Controller
August 1993
PC8477B (SuperFDC TM ) Advanced Floppy Disk Controller
General Description
The PC8477B CMOS advanced floppy disk controller is an T enhanced version of National's DP8473 floppy controller he PC8477B is software compatible with the DP8473 and NEC mPD765 floppy disk controllers In addition it is pin and software compatible with the Intel 82077AA floppy controla ler The PC8477B a 24 MHz crystal a device chip select nd a resistor package are all that is needed for a complete P TC-AT PS 2 or EISA floppy controller solution he PC8477B includes advanced features such as a 16 byte FIFO (Burst and Non-Burst modes) support of Perpendicular Recording Mode disk drives PS 2 diagnostic registers for Model 30 and Models 50 60 80 standard CMOS disk I O and additional commands to control these new features The 16 byte FIFO will increase system performance at higher data rates and with multi-tasking bus E structures This controller is designed to fit into all PC-AT ISA and PS 2 designs as well as other advanced applications F
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Pin and software compatible with Intel 82077AA FDC Software compatible with NSC's DP8473
16 byte FIFO (default disabled) Burst and Non-Burst modes Programmable threshold Perpendicular Mode Recording drive support High performance internal analog data separator (no external filter components required) Low power CMOS with manual power down mode Automatic power down mode for complete software transparency Integrates all PC-AT and PS 2 logic On chip Oscillator PC compatible FDC address decode PS 2 Model 30 and Model 50 60 80 diagnostic registers DMA control circuitry High current CMOS disk interface outputs Data Rate and Digital Output registers 12 mA mP bus interface buffers Data Rate Support 250 300 kb s 500 kb s and 1 Mb s Write precompensation software programmable 68 pin PLCC package 60 pin PQFP package Ideal for space limited applications
Functional Block Diagram
TL F 11332 3
FIGURE 1-1
SuperFDCTM is a trademark of National Semiconductor Corporation T I RI-STATE is a registered trademark of National Semiconductor Corporation C BM PC-AT and PS 2 are registered trademarks of International Business Machines Corp
1995 National Semiconductor Corporation
TL F 11332
RRD-B30M75 Printed in U S A
Table of Contents
1 0 INTRODUCTION 2 0 PIN DESCRIPTION 3 0 REGISTER DESCRIPTION 3 1 Status Register A (SRA) 3 1 1 SRA PS 2 Mode 3 1 2 SRA Model 30 Mode 3 2 Status Register B (SRB) 3 2 1 SRB PS 2 Mode 3 2 2 SRB Model 30 Mode 3 3 Digital Output Register (DOR) 3 4 Tape Drive Register (TDR) 3 5 Main Status Register (MSR) 3 6 Data Rate Select Register (DSR) 3 7 Data Register (FIFO) 3 8 Digital Input Register (DIR) 3 8 1 DIR PC-AT Mode 3 8 2 DIR PS 2 Mode 3 8 3 DIR Model 30 Mode 3 9 Configuration Control Register (CCR) 3 9 1 CCR PC-AT and PS 2 Modes 3 9 2 CCR Model 30 Mode 3 10 Result Phase Status Registers 3 10 1 Status Register 0 (ST0) 3 10 2 Status Register 1 (ST1) 3 10 3 Status Register 2 (ST2) 3 10 4 Status Register 3 (ST3) 4 0 COMMAND SET DESCRIPTION 4 1 Command Set Summary 4 2 Command Description 4 2 1 Configure Command 4 2 2 Dumpreg Command 4 2 3 Format Command 4 2 4 Invalid Command 4 2 5 Lock Command 4 2 6 Mode Command 4 2 7 NSC Command 4 2 8 Perpendicular Mode Command 4 2 9 Read Data Command 4 2 10 Read Deleted Data Command 4 2 11 Read ID Command 4 2 12 Read A Track Command 4 2 13 Recalibrate Command 4 2 14 Relative Seek Command 4 2 15 Scan Commands 4 2 16 Seek Command 4 2 17 Sense Drive Status Command 4 2 18 Sense Interrupt Command 4 2 19 Set Track Command 4 2 20 Specify Command 4 2 21 Verify Command 4 2 22 Version Command 4 2 23 Write Data Command 4 2 24 Write Deleted Data Command 5 0 FUNCTIONAL DESCRIPTION 5 1 Microprocessor Interface 5 2 Modes of Operation 5 3 Controller Phases 5 3 1 Command Phase 5 3 2 Execution Phase 5 3 2 1 DMA Mode FIFO Disabled 5 3 2 2 DMA Mode FIFO Enabled 5 3 2 3 Interrupt Mode FIFO Disabled 5 3 2 4 Interrupt Mode FIFO Enabled 5 3 2 5 Software Polling 5 3 3 Result Phase 5 3 4 Idle Phase 5 3 5 Drive Polling Phase 5 4 Data Separator 5 5 Crystal Oscillator 5 6 Dynamic Window Margin Performance 5 7 Perpendicular Recording Mode 5 8 Data Rate Selection 5 9 Write Precompensation 5 10 Low Power Mode Logic 5 11 Reset Operation 6 0 DEVICE DESCRIPTION 6 1 DC Electrical Characteristics 6 2 AC Electrical Characteristics 6 2 1 AC Test Conditions 6 2 2 Clock Timing 6 2 3 Microprocessor Read Timing 6 2 4 Microprocessor Write Timing 6 2 5 DMA Timing 6 2 6 Reset Timing 6 2 7 Write Data Timing 6 2 8 Drive Control Timing 6 2 9 Read Data Timing 7 0 REFERENCE SECTION 7 1 Mnemonic Definitions for PC8477B Commands 7 2 PC8477B Enhancements vs 82077AA 7 3 PC8477B Interface in a PC-AT 7 4 Software Initialization Sequence 7 5 PC8477B PC8477A differences 7 6 Revision History
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List of Figures
PC8477B Functional Block Diagram PC8477B Pin Diagram for 68 Pin PLCC and 60 Pin PQFP IBM Perpendicular and ISO Formats Supported by Format Command PC8477B Data Separator Block Diagram Read Data Algorithm State Diagram PC8477B Dynamic Window Margin Performance PC8477B Dynamic Window Margin Performance with g 3% ISV Perpendicular Recording Drive R W Head and Pre-Erase Head Clock Timing Microprocessor Read Timing Microprocessor Write Timing DMA Timing Reset Timing Write Data Timing Drive Control Timing Read Data Timing PC8477B in a PC-AT System PC84777B Initialization 1-1 1-2 4-1 5-1 5-2 5-3 5-4 5-5 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 7-1 7-2
List of Tables
Register Description and Addresses Drive Enable Values Tape Drive Assignment Values Write Precompensation Delays Default Precompensation Delays Data Rate Select Encoding Typical Format Gap Length Values DENSEL Encoding DENSEL Default Encoding Effects of WGATE and GAP Sector Size Selection SK Effect of Read Data Command Result Phase Termination Values with No Error SK Effect on Read Deleted Data Command Maximum Recalibrate Step Pulses Based on R255 and ETR Scan Command Termination Values Status Register 0 Termination Codes Set Track Register Address Step Rate (SRT) Values Motor Off Time (MFT) Values Motor On Time (MNT) Values Verify Command Result Phase Table Nominal tICP tDRP Values Minimum tWDW Values PC8477B 82077 Parameter Comparison Density Encoding 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 6-1 6-2 7-1 7-2
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