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Details, datasheet, quote on part number:100341
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| Part: | 100341 |
| Category: | Logic => Military/Aerospace->ECL |
| Description: | 100341 - Low Power 8-Bit Shift Register, Package: Cerquad, Pin Nb=24 |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download 100341 datasheet File size : 155 kB |
| Request For quote: | Find where to buy 100341
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Datasheet text preview:
100341 Low Power 8-Bit Shift Register
August 1998
100341 Low Power 8-Bit Shift Register
General Description
The 100341 contains eight edge-triggered, D-type flip-flops with individual inputs (Pn) and outputs (Qn) for parallel operation, and with serial inputs (Dn) and steering logic for bidirectional shifting. The flip-flops accept input data a setup time before the positive-going transition of the clock pulse and their outputs respond a propagation delay after this rising clock edge. The circuit operating mode is determined by the Select inputs S0 and S1, which are internally decoded to select either "parallel entry", "hold", "shift left" or "shift right" as described in the Truth Table. All inputs have 50 k pull-down resistors.
Features
n n n n n 35% power reduction of the 100141 2000V ESD protection Pin/function compatible with 100141 Voltage compensated operating range = -4.2V to -5.7V Standard Microcircuit Drawing (SMD) 5962-9459101
Logic Symbol
CP
Pin Names S0, S1 D0, D7 P0 P7 Q0 Q7
DS100315-1
Description Clock Input Select Inputs Serial Inputs Parallel Inputs Data Outputs
© 1998 National Semiconductor Corporation
DS100315
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Connection Diagrams
24-Pin DIP 24-Pin Quad Cerpak
DS100315-3
DS100315-2
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Logic Diagram
DS100315-5
Truth Table
Function D7 Load Register Shift Left Shift Left Shift Right Shift Right Hold Hold Hold X X X L H X X X D0 X L H X X X X X Inputs S1 L L L H H H X X S0 L H H L L H X X CP
N N N N N
Outputs Q7 P7 Q6 Q6 L H Q6 P6 Q5 Q5 Q7 Q7 Q5 P5 Q4 Q4 Q6 Q6 Q4 P4 Q3 Q3 Q5 Q5 Q3 P3 Q2 Q2 Q4 Q4 Q2 P2 Q1 Q1 Q3 Q3 Q1 P1 Q0 Q0 Q2 Q2 Q0 P0 L H Q1 Q1
X H L No Change
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care N = LOW-to-HIGH Transition
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Above which the useful life may be impaired Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) -65°C to +150°C +175°C -7.0V to +0.5V VEE to +0.5V -50 mA
ESD (Note 2)
2000V
Recommended Operating Conditions
Case Temperature (TC) Military Supply Voltage (VEE) -55°C to +125°C -5.7V to -4.2V
Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version DC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = -55°C to +125°C Symbol VOH VOL VOHC VOLC VIH VIL IIL IIH IEE Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Current Input LOW Current Input High Current Power Supply Current -168 -178 -55 -55 mA mA -55°C to +125°C -1165 Min -1025 -1085 Max -870 -870 Units mV mV mV mV mV mV -1610 -1555 -870 mV mV mV mV µA 240 340 µA µA TC 0°C to +125°C -55°C 0°C to +125°C -55°C 0°C to +125°C -55°C 0°C to +125°C -55°C -55°C to +125°C -55°C to +125°C -55°C to +125°C 0°C to +125°C -55°C Guaranteed HIGH Signal for All Inputs -1830 -1475 0.50 Guaranteed LOW Signal for All Inputs VEE = -4.2V VIN = VIL (Min) VEE = -5.7V VIN = VIH (Max) Inputs Open VEE = -4.2V to -4.8V VEE = -4.2V to -5.7V (Notes 3, 4, 5, 6) (Notes 3, 4, 5, 6) (Notes 3, 4, 5, 6) (Notes 3, 4, 5) (Notes 3, 4, 5) VIN = VIH (Min) or VIL(Max) Loading with 50 to -2.0V (Notes 3, 4, 5) VIN = VIH (Max) or VIL(Min) Loading with 50 to -2.0V (Notes 3, 4, 5) Conditions Notes
-1830 -1620 -1830 -1555 -1035 -1085
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55°C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specifications which can be considered a worst case condition at cold temperatures. Note 4: Screen tested 100% on each device at -55°C, +25°C and +125°C, Subgroups 1, 2, 3, 7, and 8. Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at -55°C, +25°C, and +125°C, Subgroups A1, 2, 3, 7, and 8. Note 6: Guaranteed by applying specified input condition and testing VOH/VOL.
AC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol fmax tPLH tPHL tTLH tTHL Parameter Max Clock Frequency Propagation Delay CP to Output Transition Time 20% to 80%, 80% to 20% 0.30 1.30 0.30 1.30 0.30 1.30 ns TC = -55°C Min 400 0.50 2.50 Max TC = +25°C Min 400 0.50 2.30 Max TC = +125°C Min 300 0.50 2.80 Max MHz ns Units Conditions Notes 4 (Notes 7, 8, 9, 11)
Figures 2, 3
Figures 1, 3
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AC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol ts Parameter Setup Time Dn, Pn Sn th Hold Time Dn, Pn Sn tpw(H) Pulse Width HIGH CP 0.90 0.50 2.00 0.60 1.70
(Continued)
TC = -55°C Min Max
TC = +25°C Min 0.60 1.60 0.90 0.50 2.00 Max
TC = +125°C Min 0.60 2.40 0.90 0.50 2.00 Max
Units
Conditions
Notes
ns
Figure 4
ns ns
(Note 10)
Figure 3
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55°C), then testing immediately after power-up. This provides "cold start" specifications which can be considered a worst case condition at cold temperatures. Note 8: Screen tested 100% on each device at +25°C temperature only, Subgroup A9. Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at +25°C, Subgroup A9, and at +125°C and -55°C temperatures, Subgroups A10 and A11. Note 10: Not tested at +25°C, +125°C and -55°C temperature (design characterization data). Note 11: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously.
Test Circuitry
DS100315-6
Notes: VCC, VCCA = +2V, VEE = -2.5V L1, L2 and L3 = equal length 50 impedance lines RT = 50 terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50 to GND CL = Fixture and stray capacitance 3 pF Pin numbers shown are for Flatpak; for DIP see logic symbol
FIGURE 1. AC Test Circuit
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