|Category||Timing Circuits => Clock Circuits|
|Description||Low Voltage PLL Clock Driver|
|Company||Motorola Semiconductor Products|
|Datasheet||Download MPC992 datasheet
The a 3.3V compatible, PLL based PECL clock generator and distributor. The fully differential design ensures optimum skew and PLL jitter performance. The performance of the device makes the MPC992 ideal for workstations, main frame computer, telecommunication and instrumentation applications. The device offers a crystal oscillator or a differential PECL reference clock input to provide flexibility in the reference clock interface. All of the control signals to the MPC992 are LVTTL compatible inputs.
Fully Integrated PLL Output Frequency to 400MHz PECL Clock Inputs and Outputs Operates from a 3.3V VCC Supply Output Frequency Configurable 32 TQFP Packaging ±25ps CycleCycle Jitter
The MPC992 offers two banks of outputs which can be configured into four different relationships. The output banks can be configured into 3:1, 3:2 and 5:2 ratios to provide a wide variety of potential frequency outputs. In addition to these two banks of outputs a synchronization output is also offered. The SYNC output will provide information as to the time when the two output banks will transition positively in phase. This information can be important when the odd ratios are used as it provides for a baseline point in the system timing. The SYNC output will pulse high for one Qa clock period, centered on the rising Qa clock edge four edges prior to the Qb synchronous edge. The relationship is illustrated in the timing diagrams in the data sheet. The MPC992 offers several features to aid in system debug and test. The PECL reference input pins can be interfaced to a test signal and the PLL can be bypassed to allow the designer to drive the MPC992 outputs directly. This allows for single stepping in a system functional debug mode. In addition an overriding reset is provided which will force all of the Q outputs LOW upon assertion. The MPC992 is packaged a 32lead TQFP package to optimize both performance and board density.PLL_EN VCO_SEL XTAL_SEL XTAL1 XTAL2 PECL_CLK FSEL0 FSEL1 POR XTAL OSC 1 0 Integrated PLL
Control Signal Reset XTAL_SEL PLL_EN VCO_SEL Logic `0' Outputs Enabled PECL REF Disabled High Frequency Logic `1' Outputs Disabled XTAL REF Enabled Low FrequencyQa 6 (fref) 8 (fref) 10 (fref) 12 (fref) Qb 4 (fref) 4 (fref) 4 (fref) 4 (fref) Int Feedback fref
Pin Name VCO_SEL PLL_EN XTAL_SEL XTAL1:2 PECL_CLK FSELn RESET Function VCO range select pin (Int Pullup) PLL bypass select pin (Int Pullup) Input reference source select pin (Int Pullup) Crystal interface pins for the internal oscillator True PECL reference clock input (Int Pulldown) Compliment PECL reference clock input (Int Pullup) Internal divider select pins (Int Pullup) Internal flipflop reset, true outputs go LOW (Int Pulldown)
Symbol VCC VI IOUT TStor Supply Voltage Input Voltage Output Current Storage Temperature Range Continuous Surge 40 Parameter Min 0.3 Max 4.6 VDD Unit mA °C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
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