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Details, datasheet, quote on part number:M2V56S20ATP-6
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Datasheet text preview:
SDRAM (Rev.1.1) Single Data Rate Aug '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
256M Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
M2V56S20ATP is a 4-bank x 16777216-word x 4-bit, M2V56S30ATP is a 4-bank x 8388608-word x 8-bit, M2V56S40ATP is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40ATP achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6), 166MHz(-5) and are suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3vą0.3V power supply - Max. Clock frequency -5:PC166 / -6:PC133 / -7:PC100 - Fully Synchronous operation referenced to clock rising edge - Single Data Rate - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/full page (programmable) - Burst type- sequential / interleave (programmable) - Random column access - Auto precharge / All bank precharge controlled by A10 - 8192 refresh cycles /64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16) - LVTTL Interface - 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
M a x . Frequency @CL2 M2V56S20/30/40ATP-5,-5L M2V56S20/30/40ATP-6,-6L M2V56S20/30/40ATP-7,-7L 133 MHz 100MHz 100 MHz M a x . Frequency @CL3 166 MHz 133 MHz 100MHz Standard PC133 (CL2) PC133 (CL3) PC100 (CL2)
MITSUBISHI ELECTRIC
1
SDRAM (Rev.1.1) Single Data Rate Aug '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
256M Synchronous DRAM PIN CONFIGURATION (TOP VIEW) x4 x8 x16
Vdd Vdd Vdd NC DQ0 DQ0 VddQ VddQ VddQ NC NC DQ1 DQ0 DQ1 DQ2 VssQ VssQ VssQ NC NC DQ3 NC DQ2 DQ4 VddQ VddQ VddQ NC NC DQ5 DQ1 DQ3 DQ6 VssQ VssQ VssQ NC NC DQ7 Vdd Vdd Vdd NC NC LDQM /WE /WE /WE /CAS /CAS /CAS /RAS /RAS /RAS /CS /CS /CS BA0 BA0 BA0 BA1 BA1 BA1 A10/AP A10/AP A10/AP A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A3 Vdd Vdd Vdd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss
Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss
Vss NC VssQ NC DQ3 VddQ NC NC VssQ NC DQ2 VddQ NC Vss NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss
CLK CKE /CS /RAS /CAS /WE DQ0-15 DQM, DQMU/L A0-12 BA0,1 Vdd VddQ Vss VssQ
: : : : : : : : : : : : : :
Master Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data I/O Output Disable / Write Mask Address Input Bank Address Input Power Supply Power Supply for Output Ground Ground for Output
MITSUBISHI ELECTRIC
2
SDRAM (Rev.1.1) Single Data Rate Aug '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
256M Synchronous DRAM DQ0-3 (x4), 0-7 (x8), 0 - 15 (x16)
BLOCK DIAGRAM
I/O Buffer
Memory Array Bank #0
Memory Array Bank #1
Memory Array Bank #2
Memory Array Bank #3
M o d e Register Control Circuitry
Address Buffer Clock Buffer A0-12 BA0,1 CLK CKE
Control Signal Buffer
/CS /RAS /CAS /WE DQMU/L
Type Designation Code
This rule is applied to only Synchronous DRAM family.
M 2 V 56 S 4 0 A TP - 5 L
Power Grade L:Low Power, Space:Standard Speed Grade 5: 166MHz@CL3, 133MHz@CL2 6: 133MHz@CL3, 100MHz@CL2 7: 100MHz@CL2 Package Type TP: TSOP(II) Process Generation A:2nd. gen. Function Reserved for Future Use Organization 2 n 2: x4, 3: x8, 4: x16 SDRAM Data Rate Type S:Single Data Rate Density 56: 256M bits Interface V:LVTTL Memory Style (DRAM) Mitsubishi Main Designation
MITSUBISHI ELECTRIC
3
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