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Details, datasheet, quote on part number:M2S56D20AKT
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Datasheet text preview:
DDR SDRAM (Rev.1.0) Jul. '01 Preliminary
M2S56D20/ 30/ 40AKT
MITSUBISHI LSIs
256M Double Data Rate Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit, M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit, M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40AKT achieves very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge; - data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Auto precharge / All bank precharge controlled by A10 - 8192 refresh cycles /64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16) - SSTL_2 Interface - 400-mil, 66-pin Thin Small Outline Package (TSOP II) - JEDEC standard
Operating Frequencies
Speed Grade -7 5 A -7 5 -1 0 Clock Rate CL=2 * 133 MHz 100 MHz 100 MHz CL=2.5 * 133 MHz 133 MHz 125 MHz * CL = CAS(Read) Latency
MITSUBISHI ELECTRIC
1
DDR SDRAM (Rev.1.0) Jul. '01 Preliminary
M2S56D20/ 30/ 40AKT
PIN CONFIGURATION(TOP VIEW) X4 X8 X 16
MITSUBISHI LSIs
256M Double Data Rate Synchronous DRAM
VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC VDDQ NC NC VDD NC NC /WE / CAS / RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDDQ NC NC VDD NC NC /WE / CAS / RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDDQ LDQS NC VDD NC LDM /WE / CAS / RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSSQ UDQS NC VREF VSS UDM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
VSS VSS DQ7 NC VSSQ VSSQ NC NC DQ6 DQ3 VDDQ VDDQ NC NC DQ5 NC VSSQ VSSQ NC NC DQ4 DQ2 VDDQ VDDQ NC NC VSSQ VSSQ DQS DQS NC NC VREF VREF VSS VSS DM DM /CLK /CLK CLK CLK CKE CKE NC NC A12 A12 A11 A11 A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 VSS VSS
64pin STSOP
PIN PITCH 0.4 mm
CLK,/CLK CKE / CS /RAS /CAS /WE DQ0 -7 DQS DM Vref
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Data Strobe : Write Mask : Reference Voltage
A0 -12 BA0,1 Vdd VddQ Vss VssQ
: Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output
MITSUBISHI ELECTRIC
2
DDR SDRAM (Rev.1.0) Jul. '01 Preliminary
M2S56D20/ 30/ 40AKT
MITSUBISHI LSIs
256M Double Data Rate Synchronous DRAM
PIN FUNCTION
SYMBOL TYPE DESCRIPTION
CLK, /CLK
Input
Clock: CLK and /CLK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of /CLK. Output (read) data is referenced to the crossings of
C L K and /CLK (both directions of crossing). C l o c k Enable: CKE controls internal clock. When CKE is low, internal clock f o r the following cycle is ceased. CKE is also used to select auto / self refresh. A f t e r self refresh mode is started, CKE becomes asynchronous input. Self refresh i s maintained as long as CKE is low. C h i p Select: When /CS is high, any command means No Operation. C o m b i n a t i o n of /RAS, /CAS, /WE defines basic commands. A 0 -1 1 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. B a n k Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data Input/Output: Data bus D a t a Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15 I n p u t Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ a n d DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7; UDM corresponds to the data on DQ8-DQ15. P o w e r Supply for the memory array and peripheral circuitry. V d d Q and VssQ are supplied to the Output Buffers only. S S T L _ 2 reference voltage.
CKE
Input
/ CS / R A S , /CAS, /WE
Input Input
A 0 -12
Input
BA0,1 D Q 0 -1 5 ( x 1 6 ) , D Q 0 -7(x8), D Q 0 -3(x4),
Input
I n p u t / Output
DQS
I n p u t / Output
DM
Input
V d d , Vss V d d Q , VssQ Vref
P o w e r Supply P o w e r Supply Input
MITSUBISHI ELECTRIC
3
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