Details, datasheet, quote on part number: DS2148T
PartDS2148T
CategoryCommunication => Network => T/E Carrier and Packetized Products
TitleT/E Carrier and Packetized Products
Description5V E1/T1/J1 Line Interface
CompanyMaxim Integrated Products
DatasheetDownload DS2148T datasheet
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Features, Applications

FEATURES

Complete or J1 line interface unit (LIU) Supports both long- and short-haul trunks Internal software-selectable receive-side termination for 75/100/120W 5V power supply or 128-bit crystal-less jitter attenuator requires only a 2.048MHz master clock for both E1 and T1 with option to use 1.544MHz for T1 Generates the appropriate line build outs, with and without return loss, for E1 and DSX-1 and CSU line build outs for T1 AMI, HDB3, and B8ZS, encoding/decoding or 2.048MHz clock output synthesized to recovered clock Programmable monitor mode for receiver Loopbacks and PRBS pattern generation/ detection with output for received errors Generates/detects in-band loop codes, to 16 bits including CSU loop codes 8-bit parallel or serial interface with optional hardware mode Multiplexed and nonmultiplexed parallel bus supports Intel or Motorola Detects/generates blue (AIS) alarms NRZ/bipolar interface for TX/RX data I/O Transmit open-circuit detection Receive Carrier Loss (RCL) indication (G.775) High-Z State for TTIP and TRING 50mA (rms) current limiter

DS21Q48 44-Pin TQFP 44-Pin TQFP 7mm CABGA 7mm CABGA (Quad) BGA (Quad) BGA to +70oC)
DESCRIPTION

The is a complete selectable or T1 Line Interface Unit (LIU) for short- and long-haul applications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts automatically to the incoming signal and can be programmed for to 43dB for E1 applications and to 36dB for T1 applications. The device can generate the necessary G.703 E1 waveshapes or 120 applications and DSX-1 line build outs or CSU line build outs -7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less onboard jitter attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can be placed in either the transmit or receive data paths. X 2.048MHz output clock synthesized to RCLK is available for use as a backplane system clock (where or 8). The DS2148 has diagnostic capabilities such as loopbacks and PRBS pattern generation/detection. 16-bit loop-up and loop-down codes can be generated and detected. The device can be controlled via an 8-bit parallel muxed or nonmuxed port, serial port or used in hardware mode. The device fully meets all of the latest E1 and T1 specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR 62411, ITU O.151, O.161, ETSI ETS TBR12, TBR13, and CTR4.

2. 3. LIST OF FIGURES............................................................................................................................... 4 LIST OF TABLES................................................................................................................................ 5 INTRODUCTION................................................................................................................................. 6 3.1 DOCUMENT REVISION HISTORY............................................................................................ 6 4. PIN DESCRIPTION............................................................................................................................. 9 5. HARDWARE MODE......................................................................................................................... 22 5.1 REGISTER MAP.......................................................................................................................... 23 5.2 PARALLEL PORT OPERATION................................................................................................ 24 5.3 SERIAL PORT OPERATION...................................................................................................... 24 6. CONTROL REGISTERS.................................................................................................................... 28 6.1 DEVICE POWER-UP AND RESET............................................................................................ 31 7 STATUS REGISTERS....................................................................................................................... 34 8. DIAGNOSTICS.................................................................................................................................. 39 8.1 IN-BAND LOOP CODE GENERATION AND DETECTION................................................... 39 8.2 LOOPBACKS............................................................................................................................... 43 8.2.1 Remote Loopback (RLB)......................................................................................................... 43 8.2.2 Local Loopback (LLB)............................................................................................................ 43 8.2.3 Analog Loopback (LLB).......................................................................................................... 44 8.2.4 Dual Loopback (DLB)............................................................................................................ 44 8.3 PRBS GENERATION AND DETECTION................................................................................. 44 8.4 ERROR COUNTER...................................................................................................................... 44 8.4.1 Error Counter Update............................................................................................................ 45 8.5 ERROR INSERTION.................................................................................................................... 45 9. ANALOG INTERFACE..................................................................................................................... 46 9.1 RECEIVER..................................................................................................................................... 46 9.2 TRANSMITTER........................................................................................................................... 47 9.3 JITTER ATTENUATOR.............................................................................................................. 9.4 G.703 SYNCHRONIZATION SIGNAL...................................................................................... 10. DS21Q48 QUAD LIU......................................................................................................................... 11. DC CHARACTERISTICS.................................................................................................................. 12. AC CHARACTERISTICS.................................................................................................................. 62 13. MECHANICAL DIMENSIONS......................................................................................................... 71 13.1 MECHANICAL DIMENSIONS--QUAD VERSION................................................................. 73


 

Related products with the same datasheet
DS2148G
DS2148GN
DS2148TN
DS21Q48
DS21Q48N
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