Details, datasheet, quote on part number: LX64ECCF2083
DescriptionHigh Performance Interfacing and Switching
CompanyLattice Semiconductor Corp.
DatasheetDownload LX64ECCF2083 datasheet


Features, Applications

High-performance sysHSI (standard part number) Low-cost, no sysHSI ("E-Series")

High bandwidth to 12.8 Gbps (SERDES) to 38 Gbps (without SERDES) 16 (15x10) FIFOs for data buffering High speed performance ­ fMAX 360MHz ­ tPD 3.0ns ­ tCO = 2.0ns Built-in programmable control logic capability I/O intensive: to 256 I/Os Expanded MUX capability to 188:1 MUX

Serializer/de-serializer (SERDES) included Clock Data Recovery (CDR) built in 800 Mbps per channel LVDS differential support 10B/12B support ­ Encoding / decoding ­ Bit alignment ­ Symbol alignment 8B/10B support ­ Bit alignment ­ Symbol alignment Source Synchronous support

Frequency synthesis and skew management Clock multiply and divide capability Clock shifting in 335ps steps Up to four PLLs

IEEE 1532 compliant In-System Programmability (ISPTM) Boundary scan test through IEEE 1149.1 interface or 1.8V power supplies 5V tolerant I/O for LVCMOS 3.3 and LVTTL interfaces

LVCMOS 2.5, 3.3 and LVTTL support for standard board interfaces SSTL 2/3 Class I and II support HSTL Class I, III and IV support GTL+, PCI-X for bus interfaces LVPECL, LVDS and Bus LVDS differential support Hot socketing Programmable drive strength Table 1. ispGDX2 Family Selection Guide

ispGDX2-64/E I/Os GDX Blocks tPD tS tCO fMAX (Toggle) Max Bandwidth sysHSI Channels PLLs Package

1. Max number of SERDES channels per device 800Mbps 2. "E-Series" does not support sysHSI. 3. fMAX (Toggle) * maximum I/Os divided by 2.

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The ispGDX2TM family is Lattice's second generation in-system programmable generic digital crosspoint switch for high speed bus switching and interface applications. The ispGDX2 family is available in two options. The standard device supports sysHSI capability for ultra fast serial communications while the lower-cost "E-series" supports the same high-performance FPGA fabric without the sysHSI Block. This family of switches combines a flexible switching architecture with advanced sysIO interfaces including high performance sysHSI Blocks, and sysCLOCK PLLs to meet the needs of the today's high-speed systems. Through a muliplexer-intensive architecture, the ispGDX2 facilitates a variety of common switching functions. The availability of on-chip control logic further enhances the power of these devices. A high-performance solution, the family supports bandwidth to 38Gbps. Every device in the family has a number of PLLs to provide the system designer with the ability to generate multiple clocks and manage clock skews in their systems.

The sysIO interfaces provide system-level performance and integration. These I/Os support various modes of LVCMOS/LVTTL and support popular high-speed standard interfaces such as GTL+, PCI-X, HSTL, SSTL, LVDS and Bus-LVDS. The sysHSI Blocks further extend this capability by providing high speed serial data transfer capability. Devices in the family can operate or 1.8V core voltages and can be programmed in-system via an IEEE 1149.1 interface that is compliant with the IEEE 1532 standard. Voltages required for the I/O buffers are independent of the core voltage supply. This further enhances the flexibility of this family in system designs. Typical applications for the ispGDX2 include multi-port multi-processor interfaces, wide data and address bus multiplexing, programmable control signal routing and programmable bus interfaces. Table 1 shows the members of the ispGDX2 family and their key features.

The ispGDX2 devices consist of GDX Blocks interconnected by a Global Routing Pool (GRP). Signals interface with the external system via sysIO banks. In addition, each GDX Block is associated with a FIFO and a sysHSI Block to facilitate the transfer of data on- and off-chip. Figure 1 shows the ispGDX2 block diagram. Each GDX Block can be individually configured in one of four modes: Basic (No FIFO or SERDES) FIFO Only SERDES Only SERDES and FIFO Each sysIO bank has its own I/O power supply and reference voltage. Designers can use any output standard within a bank that is compatible with the power supply. Any input standard may be used, providing it is compatible with the reference voltage. The banks are independent.

The ispGDX2 architecture is organized into GDX Blocks, which are connected via a Global Routing Pool. The innovative GRP is optimized for routability, flexibility and speed. All the signals enter via the GDX Block. The block supplies these either directly or in registered form to the GRP. The GRP routes the signals to different blocks, and provides separate data and control routing. The data path is optimized to achieve faster speed and routing flexibility for nibble oriented signals. The control routing is optimized to provide high-speed bit oriented routing of control signals. There are some restrictions on the allocation of pins for optimal bus routing. These restrictions are considered by the software in the allocation of pins.

The blocks are organized in a "block" (nibble) manner, with each GDX Block providing data flow and control logic for 16 I/O buffers. The data flow is organized as four nibbles, each nibble containing four Multiplexer Register Blocks (MRBs). Data for the MRBs is provided from 64 lines from the GRP. Figure 2 illustrates the groups of signals going into and out of a GDX Block. Control signals for the MRBs are provided from the Control Array. The Control Array receives the 32 signals from the GRP and generates 16 control signals: eight MUX Select, four Clock/Clock Enable, two Set/Reset and two Output Enable. Each nibble is controlled via two MUX select signals. The remaining control signals go to all the MRBs. Besides the control signals from the Control Array, the following global signals are available to the MRBs in each GDX Block: four Clock/Clock Enable, one reset/preset, one power-on reset, two of four MUX select (two of two in 64 I/O), four Output Enable (two in 64 I/O) and Test Out Enable (TOE).


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