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Details, datasheet, quote on part number:PDM41532SA-15I
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Datasheet text preview:
PRELIMINARY
PDM41532
64K x 16 CMOS Static RAM
Features
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Description
The PDM41532 is a high-performance CMOS static RAM organized as 65,536 x 16 bits. The PDM41532 features low power dissipation using chip enable (CE) and has an output enable input (OE) for fast memory access. Byte access is supported by upper and lower byte controls. The PDM41532 operates from a single 5.0V power supply and all inputs and outputs are fully TTLcompatible. The PDM41532 comes in two versions, the standard power version PDM41532SA and a low power version PDM41532LA. The two versions are functionally the same and only differ in their power consumption. The PDM41532 is available in a 44-pin 400 mil plastic SOJ and a 44-pin plastic TSOP (II) package suitable for high-density surface assembly and is suitable for use in high-speed applications such as cache memory and high-speed storage.
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High-speed access times - Com'l: 10, 12, 15 and 20 ns - Ind: 12, 15 and 20 ns Low power operation (typical) - PDM41532SA Active: 350 mW Standby: 50 mW - PDM41532LA Active: 300 mW Standby: 25mW High-density 64K x 16 architecture Single +5V (±10%) power supply Fully static operation TTL-compatible inputs and outputs Output buffer controls: OE Data byte controls: LB, UB Packages: Plastic SOJ (400 mil) - SO Plastic TSOP (II) - T
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Functional Block Diagram
Row Address Buffer Row Decoder Vcc Vss
A8-A0
Memory C A ell 2 rray 56 x 128 x 32
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I/O15-I/O0
IData O put/ n Butput uffer
Sense Amp
D olumn C ecoder WE OE UB LB CE
Control L ogic G Clock enerator
A olumn C B dress d uffer
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A15-A9
Rev. 1.3 - 4/10/98
PRELIMINARY
PDM41532
Pin Configuration TSOP (II)
A4 A3 A2 A1 C0 IE I/O0 I/O1 I/O2 V3 /O Vcc I ss I/O4 I/O5 I/O6 /O7 W AE A15 A14 A13 N2 1 C 1 2 3 4 5 6 7 8 9 10 11 12 3 14 15 16 17 18 19 20 21 12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 O7 UE LB IB I/O15 I/O14 I/O13 VO12 / Vss I cc I/O11 I/O10 I/O9 NO8 / AC A8 A9 A10 N11 C
SOJ
A4 A3 A2 A1 C0 IE I/O0 I/O1 I/O2 V3 /O Vcc I ss I/O4 I/O5 I/O6 /O7 W AE A15 A14 A13 N2 1 C 1 2 3 4 5 6 7 8 9 10 11 12 3 14 15 16 17 18 19 20 21 12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 O7 UE LB IB I/O15 I/O14 I/O13 VO12 / Vss I cc I/O11 I/O10 I/O9 NO8 / AC A8 A9 A10 N11 C
Pin Description
Name A15-A0 I/O15-I/O0 CE WE OE LB, UB NC VSS VCC Description Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Data Byte Control Inputs No connect Ground Power (+5V)
Capacitance (TA = +25°C, f = 1.0 MHz)
Symbol CIN CI/O Parameter Input Capacitance Output Capacitance Conditions VIN = VSS VI/O = VSS Max. 6 8 Unit pF pF
NOTE: 1. This parameter is determined by device characterization, but is not production tested.
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Rev. 1.3 - 4/10/98
PRELIMINARY
PDM41532
Operating Mode
Mode Read CE L OE L WE H LB L H L Write L X L L H L Output Disable L L Standby H H X X H X X X H X UB L L H L L H x H X I/O7-I/O0 Output High Impedance Output Input High Impedance Input High Impedance High Impedance High Impedance I/O15-I/O8 Output Output High Impedance Input Input High Impedance High Impedance High Impedance High Impedance Power ICC ICC ICC ICC ICC ICC ICC ICC ISB
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NOTE: 1. H = VIH, L = VIL, X = DON'T CARE
Absolute Maximum Ratings (1)
Symbol VTERM TBIAS TSTG PT IOUT Tj Rating Terminal Voltage with Respect to VSS Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Maximum Junction Temperature (2) Com'l. 0.5 to +7.0 55 to +125 55 to +125 1.5 50 125 Ind. 0.5 to +7.0 65 to +135 65 to +150 1.5 50 145 Unit V °C °C W mA °C
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NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Appropriate thermal calculations should be performed in all cases and specifically for those where the chosen package has a large thermal resistance (e.g., TSOP). The calculation should be of the form: Tj = Ta + P * ja where Ta is the ambient temperature, P is average operating power and ja the thermal resistance of the package. For this product, use the following ja values: SOJ: 59o C/W TSOP: 87o C/W
Rev. 1.3 - 4/10/98
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