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Details, datasheet, quote on part number:PDM34089SA10QTY
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Datasheet text preview:
PRELIMINARY
PDM34089
3.3V 64K x 32 Fast CMOS Synchronous Static RAM with Burst Counter
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Features
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Description
The PDM34089 is a 2,097,152 bit synchronous random access memory organized as 65,536 x 32 bits. It is designed with burst mode capability and interface controls to provide high-performance in second level cache designs for x86, Pentium, 680x0, and PowerPC microprocessors. Addresses, write data and all control signals except output enable are controlled through positive edge-triggered registers. Write cycles are self-timed and are also initiated by the rising edge of the clock. Controls are provided to allow burst reads and writes of up to four words in length. A 2-bit burst address counter controls the two least-significant bits of the address during burst reads and writes. The burst address counter selectively uses the 2-bit counting scheme required by the x86 and Pentium or 680x0 and PowerPC microprocessors as controlled by the mode pin. Individual write strobes provide byte write for the four 8-bit bytes of data. An asynchronous output enable simplifies interface to high-speed buses.
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Interfaces directly with the x86, PentiumTM, 680X0 and PowerPCTM processors Single 3.3V power supply Mode selectable for interleaved or linear burst: Interleaved for x86 and Pentium Linear for 680x0 and PowerPC Fast access times: 9, 10, 12 and 15 ns High-density 64K x 32 architecture with burst address counter Fully registered inputs High-output drive: 30 pF at rated TA Asynchronous output enable Self-timed write cycle Separate byte write enables and one global write enable Internal burst read/write address counter Internal registers for address, data, controls Burst mode selectable Sleep mode Packages: 100-pin QFP - (Q) 100-pin TQFP - (TQ)
TM
i486, Pentium are trademarks of Intel Corp. PowerPC is a trademark of the International Business Machines Corporation. 1
Rev 1.1 - 5/01/98
PRELIMINARY
PDM34089
Functional Block Diagram
A15-A0 16
R DDRESS A EGISTER
16
14
16
A1,A0 MODE
ADV
CLK
Q0
A0'
C BURST A OUNTER ND LOGIC
CLR Q1
A1'
ADSC ADSP BW1
8
BYTE 1 WRITE REGISTER
8
BYTE 4 WRITE DRIVER
8
BW2
BYTE 2 WRITE REGISTER
8
BYTE 3 WRITE DRIVER
8
BW3
2K x 32 MEMORY A 3 RRAY
32
OUTPUT B UFFER
32 DQ32-DQ1
BYTE 3 WRITE REGISTER
8
BYTE 2 WRITE DRIVER
8
BW4 BWE GW CE
CE2
BYTE 4 WRITE REGISTER
BYTE 1 WRITE DRIVER
8
RENABLE EGISTER
CE2 OE
R INPUT EGISTERS
2
Rev 1.1 - 5/01/98
PRELIMINARY
PDM34089
PDM34089 Pinout
A6 C7 CE B E2 BW4 BW3 BW2 CW1 V E2 VCC CSS GLK BW OWE AE ADSC ADSP ADV A8 9
1
7 80 79 78 77 76 75 74 73 72 71 60 69 68 67 66 65 64 63 62 61 50 59 58 57 56 55 54 53 52 1 NC DQ16 V Q15 VCCQ DSSQ DQ14 DQ13 DQ12 V Q11 VSSQ DCCQ DQ10 V Q9 NSS VC Z CC DZ DQ8 V Q7 VCCQ DSSQ DQ6 DQ5 DQ4 V Q3 VSSQ DCCQ DQ2 NQ1 C
3
00 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 D NC DQ17 V 18 Q VCCQ D SSQ DQ19 DQ20 DQ21 V 22 Q V SSQ D CCQ DQ23 QF4 2 VT NC C VC D SS DQ25 V 26 Q VCCQ D SSQ DQ27 DQ28 DQ29 V 30 Q V SSQ D CCQ DQ31 Q32 N C 2 1 3 4 5 6 7 8 9 1 10 11 12 13 14 15 16 17 18 29 20 21 22 23 24 25 26 27 28 39 0 1 1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2 3 4 5 6 7 8 9 10 11 12
Rev 1.1 - 5/01/98
MODE A A5 A4 A3 A2 A1 N0 NC VC V SS NC C NC AC A10 A11 A12 A13 A14 N5 1 C
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