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Details, datasheet, quote on part number:HMU17/883
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Datasheet text preview:
®
December 1999
UCT T PROD ODUC OLETE STITUTE PR r at OB S e nt e SUB pport C c SI B L E A POS echnical Su tersil.com/ts FOR our T or www.in t 16 c o n t a c T ER SI L 888-IN 1-
HMU17/883
x 16-Bit CMOS Parallel Multiplier
Features
· This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. · 16 x 16-Bit Parallel Multiplier with Full 32-Bit Product · High-Speed (45ns) Clocked Multiply Time · Low Power CMOS Operation - IC CSB = 500µA Maximum - IC COP = 7.0mA Maximum at 1MHz · HMU 17/883 is Compatible with the AM29517, LMU17, IDT7217, and the CY7C517 · Supports Two's Complement, Unsigned Magnitude and Mixed Mode Multiplication · TTL Compatible Inputs/Outputs - Three-State Output
Description
The HMU17/883 is a high speed, low power CMOS 16 x 16-bit parallel multiplier ideal for fast, real time digital signal processing applications. The 16-bit X and Y operands may be independently specified as either two's complement or unsigned magnitude format, thereby allowing mixed mode multiplication operations. Additional inputs are provided to accommodate format adjustment and rounding of the 32-bit product. The Format Adjust control allows the user the option of selecting a 31-bit product with the sign bit replicated LSP. The Round control is provided to accommodate rounding of the most significant portion of the result. This is accomplished by adding one to the most significant bit of the LSP. Two 16-bit output registers (MSP and LSP) are provided to hold the most and least significant portions of the result, respectively. These registers may be made transparent for asynchronous operation through the use of the Feedthrough Control (FT). The two halves of the product may be routed to a single 16-bit threestate output port via the output multiplexer control, and in addition, the LSP is connected to the Y-input port through a separate three-state buffer. The HMU17/883 utilizes a single clock signal (CLK) along with three register enables (ENX, ENY, and ENP) to latch the input operands and the output product registers. The ENX and ENY inputs enable the X and Y input registers, while ENP enables both the LSP and MSP output registers. This configuration facilitates the use of the HMU17/883 for micro-programmed systems. All outputs of the HMU17/883 also offer three-state control for multiplexing onto multiuse system busses.
Ordering Information
PA RT NUMBER HMU17GM-45/883 HMU17GM-60/883 TEMP. RANGE (o C ) -55 to 125 -55 to 125 P ACKAGE 68 Ld PGA 68 Ld PGA
Functional Block Diagram
X0-15 TCX RND TCY Y0-15/P0-15
REGISTER
REGISTER
REGISTER OEL
CL K ENX ENY MULTIPLIER ARRAY
FA FT
FORMAT ADJUST MSP REGI STER LSP REGI STER
E NP MSPSEL OEP P1 6-31/P0 -1 5 MULTIPLEXER
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2805.3
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HMU17/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V Input or Output Voltage Applied . . . . . . . . . GND 0.5V to VCC +0.5V ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA ( oC/W) JC (oC/W) PGA Package . . . . . . . . . . . . . . . . . . . 42.69 10.0 Maximum Package Power Dissipation at 125 PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.17 Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . - 65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V Temper ature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Die Characteristics
Number of Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4,500
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. D C ELECTRICAL PERFORMANCE SPECIFICATIONS PA RAME TER Logical One Input V oltage Logical Zero Input V oltage Output HIGH Voltage Output LOW Voltage Input Leakage Current Output or I/O Leakage Current S tandby Power Supply Current Operating Power Supply Current SYMBOL VIH V IL V OH VOL II IO ICCSB TE ST CONDITIONS VCC = 5.5V VCC = 4.5V IOH = 400µA VCC = 4.5V (Note 2) IOL = +4.0mA VCC = 4.5V (Note 2) VIN = VCC or GND VCC = 5.5V VOUT = VCC or GND VCC = 5.5V VIN = VCC or GND, VCC = 5.5V, Outputs Open f = 1.0 MHz, VIN = VCC or GND VCC = 5.5V ( Note 3) ( Note 4) GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 TEMPERATURE (oC) - 55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 2.2 2.6 -1 0 -1 0 M AX 0.8 0.4 +10 +10 500 UNITS V V V V µA µA µA
ICCOP
1, 2, 3
-55 TA 125
-
7.0
mA
Functional Test NOTES :
FT
7, 8
-55 TA 125
-
-
2. Interchanging of force and sense conditions is permitted. 3. Operating Supply Current is proportional to frequency, typical rating is 5mA/MHz. 4. Tested as follows: f = 1MHz, VIH (Clock Inputs) = 3.0, VIH (All other inputs) = 2.6, V IL = 0.4, VOH 1.5V, and VOL 1.5V.
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HMU17/883
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested GR OUP A SUBGR OUP S 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 ( Note 6) 9, 10, 11 9, 10, 11 - 45 -6 0
PA RAME TER Unclocked Multiply Time Clocked Multiply Time X , Y, RND Setup Time Clock HIGH Pulse Width Clock LOW Pulse Width MSP SEL to Product Out Output Clock to P Output Clock to Y Three- State Enable Time Clock Enable Setup
SYMBOL t MUC tMC tS tPWH tPWL t PDSEL tPDP tPDY tENA tSE
(NOTE 1) CONDITIONS
TEMPER ATURE (o C ) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125
MIN 18 15 15 15
M AX 70 45 25 25 25 25 -
MIN 20 20 20 15
MA X 90 60 30 30 30 30 -
UNITS ns ns ns ns ns ns ns ns ns ns
NOTES: 5. AC Testing as follows: VCC = 4.5V and 5.5V. Input levels 0V and 3.0V; Timing reference levels = 1.5V; output load per test load circuit, with V1 = 2.4V, R1 = 500 and C L = 40pF. 6. Transition is measured at ±200mV from steady state voltage, output loading per test load circuit, with V1 = 1.5V, R1 = 500 and CL = 40pF. TABLE 3. ELEC TRICAL PERFORMANCE SPECIFICATIONS -45 PA RAME TER Input Capacitance Output Capacitance I/O Capacitance X , Y, RND Hold Time Three- State Disable Time Clock Enable Hold Time Output Rise Time Output Fall Time NOTES : 7. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 8. Guaranteed, but not 100% tested. 9. Transition is measured at ±200mV from steady state voltage; output loading per test load circuit; with V 1 = 1.5V, R1 = 500 and C L = 40pF. 10. Loading is as specified in the test load circuit, with V1 = 2.4V, R1 = 500 and C L = 40pF. SYMBOL C IN COUT C I/O tH tDIS tHE tR tF From 0.8V to 2.0V From 2.0V to 0.8V CONDITIONS VCC = Open, f = 1MHz A ll Measurements are referenced to device GND. NOTES 7 7 7 7, 8 7, 8, 9 7, 8, 9 7, 8, 10 7, 8, 10 TEMPERA TURE (oC) TA = 25 TA = 25 TA = 25 - 55 TA 125 - 55 TA 125 - 55 TA 125 - 55 TA 125 - 55 TA 125 MIN 3 3 M AX 15 10 10 25 10 10 MIN 3 3 -60 M AX 15 10 10 30 10 10 UNITS pF pF pF ns ns ns ns ns
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