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Details, datasheet, quote on part number:HM-6617
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Datasheet text preview:
TM
HM-6617
2K x 8 CMOS PROM
Description
The HM-6617 is a 16,384 bit fuse link CMOS PROM in a 2K word by 8-bit/word format with "Three-State" outputs. This PROM is available in the standard 0.600 inch wide 24 pin SBDIP, the 0.300 inch wide slimline SBDIP, and the JEDEC standard 32 pad CLCC. The HM-6617 utilizes a synchronous design technique. This includes on-chip address latches and a separate output enable control which makes this device ideal for applications utilizing recent generation microprocessors. This design technique, combined with the Intersil advanced self-aligned silicon gate CMOS process technology offers ultra-low standby current. Low ICCSB is ideal for battery applications or other systems with low power requirements. The Intersil NiCr fuse link technology is utilized on this and other Intersil CMOS PROMs. This gives the user a PROM with permanent, stable storage characteristics over the full industrial and military temperature voltage ranges. NiCr fuse technology combined with the low power characteristics of CMOS provides an excellent alternative to standard bipolar PROMs or NMOS EPROMs. All bits are manufactured storing a logical "0" and can be selectively programmed for a logical "1" at any bit location.
March 1997
Features
· Low Power Standby and Operating Power - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100µA - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz Fast Access Time . . . . . . . . . . . . . . . . . . . . . . 90/120ns Industry Standard Pinout Single 5.0V Supply CMO S/TTL Compatible Inputs High Output Drive . . . . . . . . . . . . . . . . 12 LSTTL Loads Synchronous Operation On-Chip Address Latches Separate Output Enable
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Ordering Information
PACKAGE SBDIP SMD# SLIM SBDIP SMD# CLCC SMD# TEMP. RANGE 90ns 120ns PKG. NO. D24.6 D24.6 D24.3 D24.3 J32.A -40oC to +85oC HM1-6617B- HM19 6617-9 -55oC to +125oC 59628954002JA 59628954001JA
-40oC to +85oC HM6-6617B- HM69 6617-9 -55oC to +125oC 59628954002LA 59628954001LA
-40oC to +85oC HM4-6617B- HM49 6617-9
5962J32.A -55oC to +125oC 59628954002XA 8954001XA
Pinouts
HM-6617 (SBDIP) TOP VIEW
A7 A7 A6 A5 A4 A3 A2 A1 A0 Q0 1 2 3 4 5 6 7 8 9 24 VCC 23 A8 22 A9 21 P 20 G 19 A10 18 E 17 Q7 16 Q6 15 Q5 14 Q4 13 Q3 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 Q0 13 14 15 16 17 1 8 19 20 Q1 Q2 Q3 Q4 G ND NC Q5
HM-6617 (CLCC) TOP VIEW
VCC NC NC NC NC NC
PIN DESCRIPTION PIN
29 A8 28 A9 27 NC 26 P 25 G 24 A10 23 E 22 Q7 21 Q6
DESCRIPTION No Connect Address Inputs Chip Enable Data Output Power (+5V) Output Enable Output Enable
4
3
2
1
3 2 31 30
NC A0-A10 E Q VCC G P (Note)
Q1 10 Q2 11 GND 12
NOTE: P should be hardwired to VCC except during programming.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN3017.1
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HM-6617 Functional Diagram
MSB A10 A9 A8 A7 A6 A5 A4 A LATCHED ADDRESS REGISTER A LSB L 7 Q2 G 16 1 6 16 16 1 6 16 16 1 6 E G GATED COLUMN DECODER AND DATA OUTPUT CONTROL A 4 G ALL LINES POSITIVE LOGIC: ACTIVE HIGH L A 4 Q6 LATCHED ADDRESS REGISTER LSB A3 A2 A1 A0 Q7 8 Q3 Q4 Q5 7 GATED RO W DECODER 1 28 x 128 MATRIX Q0 Q1
12 8
THREE-STATE BUFFERS: A HIGH OUTPUT ACTIVE ADDRESS LATCHES AND GATED DECODERS: LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF G
MSB
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HM-6617 Background Information Programming Algorithm
The HM-6617 CMOS PROM is manufactured with all bits containing a logical zero (output low). Any bit can be programmed selectively to a logical one (output high) state by following the procedure shown below. To accomplish this, a programmer can be built that meets the specifications shown, or any of the approved commercial programmers can be used. Programming Sequence Of Events 1. Apply a voltage of VC C1 to VCC of the PROM. 2. Read all fuse locations to verify that the PROM is blank (output low). 3. Place the PROM in the initial state for programming: E = VIH , P = VIH , G = VIL. 4. Apply the correct binary address for the word to be programmed. No inputs should be left open circuit. 5. After a delay of tD, apply voltage of VIL to E (pin 18) to access the addressed word. 6. The address may be held through the cycle, but must be held valid at least for a time equal to tD after the falling edge of E. None of the inputs should be allowed to float to an invalid logic level. 7. After a delay of tD, disable the outputs by applying a voltage of VIH to G (pin 20). 8. After a delay of tD, apply voltage of VIL to P (pin 21). 9. After delay of tD, raise VCC (pin 24) to VCCPROG with a rise time of tR. All outputs at VIH should track VCC with VCC -2.0V to VC C +0.3V. This could be accomplished by pulling outputs at V IH to VCC through pull-up resistors of value Rn. 10. After a delay of tD, pull the output which corresponds to the bit to be programmed to VIL. Only one bit should be programmed at a time. 11. After a delay of tPW, allow the output to be pulled to VIH through pull-up resistor Rn. 12. After a delay of tD, reduce VCC (pin 24) to VCC1 with a fall time of tF. All outputs at VIH should track VCC with VCC 2.0V to VCC +0.3V. This could be accomplished by pulling outputs at VIH to VCC through pull-up resistors of value Rn. 13. Apply a voltage of VIH to P (pin 21). 14. After a delay of tD, apply a voltage of VIL to G (pin 20). 15. After a delay of tD, examine the outputs for correct data. If any location verifies incorrectly, repeat steps 4 through 14 (attempting to program only those bits in the word which verified incorrectly) up to a maximum of eight attempts for a given word. If a word does not program within eight attempts, it should be considered a programming reject. 16. Repeat steps 3 through 15 for all other bits to be programmed in the PROM. Post-Programming Verification 17. Place the PROM in the post-programming verification mode: E = VIH , G = VIL, P = VIH , V C C (pin 24) = VCC 1. 18. Apply the correct binary address of the word to be verified to the PROM. 19. After a delay of tD, apply a voltage of V IL to E (pin 18). 20. After a delay of tD, examine the outputs for correct data. If any location fails to verify correctly, the PROM should be considered a programming reject. 21. Repeat steps 17 through 20 for all possible programming locations Post-Programming Read 22. Apply a voltage of VCC2 = 4.0V to VCC (pin 24). 23. After a delay of tD, apply a voltage of V IH to E (pin 18). 24. Apply the correct binary address of the word to be read. 25. After a delay of TAVEL, apply a voltage of VIL to E (pin 18). 26. After a delay of TELQV, examine the outputs for correct data. If any location fails to verify correctly, the PROM should be considered a programming reject. 27. Repeat steps 23 through 26 for all address locations. 28. Apply a voltage of VCC2 = 6.0V to VCC (pin 24). 29. Repeat steps 23 through 26 for all address locations.
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