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Details, datasheet, quote on part number:HM-65642883
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Datasheet text preview:
HM-65642/883
March 1997
8K x 8 Asynchronous CMOS Static RAM
Description
The HM-65642/883 is a CMOS 8192 x 8-bit Static Random Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide standard, which allows easy memory board layouts which accommodate a variety of industry standard ROM, PROM, EPROM, EEPROM and RAMs. The HM-65642/883 is ideally suited for use in microprocessor based systems. In particular, interfacing with the Intersil 80C86 and 80C88 microprocessors is simplified by the convenient output enable (G) input. The HM-65642/883 is a full CMOS RAM which utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temperature range. In addition to this, the high stability of the 6T RAM cell provides excellent protection against soft errors due to noise and alpha particles. This stability also improves the radiation tolerance of the RAM over that of four transistor or MIX-MOS (4T) devices
Features
· This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. · Full CMOS Design · Six Transistor Memory Cell · Low Standby Supply Current . . . . . . . . . . . . . . . .100µA · Low Operating Supply Current . . . . . . . . . . . . . . . 20mA · Fast Address Access Time . . . . . . . . . . . . . . . . . . 150ns · Low Data Retention Supply Voltage. . . . . . . . . . . . 2.0V · CMOS/TTL Compatible Inputs/Outputs · JEDEC Approved Pinout · Equal Cycle and Access Times · No Clocks or Strobes Required · Gated Inputs - No Pull-Up or Pull-Down Resistors Required · Temperature Range -55oC to +125oC · Easy Microprocessor Interfacing · Dual Chip Enable Control
Ordering Information
PACKAGE CERDIP CLCC TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC 150ns/75µA HM1-65642B/883 HM4-65642B/883 150ns/150µA HM1-65642/883 HM4-65642/883 200ns/250µA HM1-65642C/883 PKG. NO. F28.6 J32.A
Pinouts
HM-65642/883 (CERDIP) TOP VIEW
NC 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 DQ0 11 DQ1 12 DQ2 13 GND 14 28 VCC 27 W 26 E2 25 A8 24 A9 23 A11 22 G 21 A10 20 E1 19 DQ7 18 DQ6 17 DQ5 16 DQ4 15 DQ3 A6 A5 A4 A3 A2 5 6 7 8 9
HM4-65642/883 (CLCC) TOP VIEW
VCC A12 NC NC A7 E2 W
4
3
2
1
32
31
30 29 A8 28 A9 27 A11 26 NC 25 G 24 A10 23 E1 22 DQ7 21 DQ6
PIN A DQ E1 E2 W G NC GND VCC
DESCRIPTION Address Input Data Input/Output Chip Enable Chip Enable Write Enable Output Enable No Connections Ground Power
A1 10 A0 11 NC 12 DQ0 13 14 DQ1 15 16 DQ2 GND 17 NC 18 DQ3 19 DQ4 20 DQ5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number
3004.1
6-220
HM-65642/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage Applied for all Grades . . . . . . .GND -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . . . . 5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical) JA JC CERDIP Package . . . . . . . . . . . . . . . . 45oC/W 8oC/W CLCC Package . . . . . . . . . . . . . . . . . . 55oC/W 10oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101,000 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . +2.2V to VCC +0.3V Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max.
TABLE 1. HM-65642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current SYMBOL VOH 1 (NOTE 1) CONDITIONS VCC = 4.5V, IO = -1.0mA GROUP A SUBGROUPS 1, 2, 3 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 2.4 MAX UNITS V
VOL
VCC = 4.5V, IO = 4.0mA
1, 2, 3
-
0.4
V µA
IIOZ
HM-65642B/883, HM-65642/883 VCC = 5.5V, G = 2.2V, VI/O = GND or VCC HM-65642C/883 VCC = 5.5V, G = 2.2V, VI/O = GND or VCC
1, 2, 3
-1.0
+1.0
1, 2, 3
-55oC TA +125oC
-2.0
+2.0
µA
Input Leakage Current
II
HM-65642B/883, HM-65642/883 VCC = 5.5V, VI = GND or VCC HM-65642C/883 VCC = 5.5V, VI = GND or VCC
1, 2, 3
-55oC TA +125oC -55oC TA +125oC -55oC TA +125oC
-1.0
+1.0
µA µA µA
1, 2, 3
-2.0
+2.0
Standby Supply Current
ICCSB1
HM-65642B/883 VCC = 5.5V, E1 = VCC -0.3V or E2 = GND +0.3V HM-65642/883 VCC = 5.5V, E1 = VCC -0.3V or E2 = GND +0.3V HM-65642C/883 VCC = 5.5V, E1 = VCC -0.3V or E2 = GND +0.3V
1, 2, 3
-
100
1, 2, 3
-55oC TA +125oC
-
250
µA
1, 2, 3
-55oC TA +125oC
-
400
µA
Standby Supply Current Enable Supply Current Operating Supply Current
ICCSB
VCC = 5.5V, IO = 0mA, E1 = 2.2V or E2 = 0.8V VCC = 5.5V, IO = 0mA, E1 =0.8V, E2 = 2.2V VCC = 5.5V, G = 5.5V, (Note 2), f = 1MHz, E1 = 0.8V, E2 = 2.2V
1, 2, 3
-55oC TA +125oC -55oC TA +125oC -55oC TA +125oC
-
5
mA
ICCEN
1, 2, 3
-
5
mA
ICCOP
1, 2, 3
-
20
mA
6-221
HM-65642/883
TABLE 1. HM-65642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed and 100% Tested LIMITS PARAMETER Data Retention Supply Current SYMBOL ICCDR (NOTE 1) CONDITIONS HM-65642B/883 VCC = 2.0V, E1 = VCC -0.3V or E2 = GND +0.3V HM-65642/883 VCC = 2.0V, E1 = VCC -0.3V or E2 = GND +0.3V HM-65642C/883 VCC = 2.0V, E1 = VCC -0.3V or E2 = GND +0.3V Functional Test NOTES: 1. All voltages referenced to device GND. 2. Typical derating 5mA/MHz increase in ICCOP. 3. Tested as follows: f = 2MHz, VIH = 2.4V, VIL = 0.4V, IOH = -4.0mA, IOL = 4.0mA, VOH 1.5V, and VOL 1.5V. TABLE 2. HM-65642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
LIMITS GROUP A SUBGROUPS 9, 10, 11 HM65642B/883 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 150 MAX HM65642/883 MIN 150 MAX HM65642C/883 MIN 200 MAX UNITS ns
GROUP A SUBGROUPS 1, 2, 3
TEMPERATURE -55oC TA +125oC
MIN -
MAX 75
UNITS µA
1, 2, 3
-55oC TA +125oC
-
150
µA
1, 2, 3
-55oC TA +125oC
-
250
µA
FT
VCC = 4.5V (Note 3)
7, 8A, 8B
-55oC TA +125oC
-
-
-
PARAMETERS Read/Write/ Cycle Time Address Access Time Output Enable Access Time Chip Enable Access Time Write Recovery Time
SYMBOL TAVAX
(NOTES 1, 2) CONDITIONS VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V
TAVQV
9, 10, 11
-
150
-
150
-
200
-
TGLQV
9, 10, 11
-
70
-
70
-
70
ns
TE1LQV TE2HQV TWHAX TE1HAX TE2LAX TE1LE1H TE2HE2L TAVWL TAVE1L TAVE2H TWLWH
9, 10, 11
-
150
-
150
-
200
ns
9, 10, 11
10
-
10
-
10
-
ns
Chip Enable to End-of-Write Address Setup Time
VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V
9, 10, 11
-55oC TA +125oC -55oC TA +125oC
90
-
90
-
120
-
ns
9, 10, 11
0
-
0
-
0
-
ns
Write Enable Pulse Width Data Setup Time
VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V
9, 10, 11
-55oC TA +125oC -55oC TA +125oC
90
-
90
-
120
-
ns
TDVWH TDVE1H TDVE2L
9, 10, 11
60
-
60
-
80
-
ns
6-222
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