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Details, datasheet, quote on part number:HM-65642
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Datasheet text preview:
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HM-65642
8K x 8 Asynchronous CMOS Static RAM
Description
The HM-65642 is a CMOS 8192 x 8-bit Static Random Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide standard, which allows easy memory board layouts which accommodate a variety of industry standard ROM, PROM, EPROM, EEPROM and RAMs. The HM-65642 is ideally suited for use in microprocessor based systems. In particular, interfacing with the Intersil 80C86 and 80C88 microprocessors is simplified by the convenient output enable (G) input. The HM-65642 is a full CMOS RAM which utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temperature range.
May 2002
Features
· Full CMOS Design · Six Transistor Memory Cell · Low Standby Supply Current . . . . . . . . . . . . . . . . 100µA · Low Operating Supply Current. . . . . . . . . . . . . . . 20mA · Fast Address Access Time . . . . . . . . . . . . . . . . . . 150ns · Low Data Retention Supply Voltage . . . . . . . . . . . 2.0V · CMOS/TTL Compatible Inputs/Outputs · JEDEC Approved Pinout · Equal Cycle and Access Times · No Clocks or Strobes Required · Gated Inputs · No Pull-Up or Pull-Down Resistors Required · Easy Microprocessor Interfacing · Dual Chip Enable Control
Ordering Information
P ACKAGE CERDIP JA N # TEMPERATURE RANGE -40oC to +85oC -55oC to +125oC 29205B XA (NOTE 1) 150ns/75µA (NOTE 1) 150ns/150µA H M 1 -6 5 6 4 2 - 9 (NOTE 1) 200ns/250µA PKG. NO. F28.6 F28.6
NOTE: 1. Access Time/Data Retention Supply Current.
Pinout
HM-65642 (CERDIP) TOP VIEW
NC 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 DQ0 11 DQ1 12 DQ2 13 GND 14 28 VCC 27 W 26 E2 25 A8 24 A9 23 A11 22 G 21 A10 20 E1 19 DQ7 18 DQ6 17 DQ5 16 DQ4 15 DQ3
PIN A DQ E1 E2 W G NC G ND VCC
DESCRIPTION Address Input Data Input/Output Chip Enable Chip Enable Write Enable Output Enable No Connections G ro und P ower
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN3005.2
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HM-65642 Functional Diagram
A9 RO W ADDRESS BUFFERS A8 A12 A7 A6 A5 A4 A3 A RO W DECODER 8 256
256 x 256 MEMORY ARRAY
A 8
256 COLUMN ADDRESS BUFFERS A2 A1 A0 A10 A11
A 5 A 5 COLUMN SELECT (8 OF 256)
8 W
G
E1
8 E2 1 OF 8 DQ
TRUTH TABLE MO DE Standby (CMOS) Standby (TTL) E1 X VIH X Enable (High Z) W ri t e Read VI L VIL VI L E2 G ND X VIL VIH VIH VIH W X X X VIH VIL VIH G X X X VIH X VIL
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HM-65642
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage Applied for All Grades . . . . . . GND -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . . . 5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
JC Thermal Resistance (Typical) JA CERDIP Package . . . . . . . . . . . . . . . . 45oC/W 8oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101,000 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-65642-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . +2.2V to VCC +0.3V
DC Electrical Specifications
SYMBOL I CCS B1 I CCS B2 I CCDR I CCEN I CCO P II IIOZ V CCDR VOH1 VOH2 VOL
VCC = 5V ±10%; TA = -40oC to +85oC (HM-65642-9) LIMITS
PARAMETER Standby Supply Current (CMOS) Standby Supply Current (TTL) Data Retention Supply Current Enabled Supply Current Operating Supply Current (Note 1) Input Leakage Current Input/Output Leakage Current Data Retention Supply Voltage Output High Voltage Output High Voltage (Note 2) Output Low Voltage TA = +25oC PARAMETER Input Capacitance (Note 2) Input/Output Capacitance (Note 2)
MIN -1. 0 -1. 0 2. 0 2. 4 VCC -0.4 -
M AX 250 5 150 5 20 +1.0 +1.0 0. 4
UNITS µA mA µA mA mA µA µA V V V V
TEST CONDITIONS E2 = GND, VCC = 5.5V E2 = 0.8V or E1 = 2.2V, VCC = 5.5V E2 = GND, VCC = 2.0V E2 = 2.2V, E1 = 0.8V, VCC = 5.5V, IIO = 0mA f = 1MHz, E1 = 0.8V, E2 = 2.2V, VCC = 5.5V, IIO = 0mA VI = VCC or GND, VCC = 5.5V E2 = GND, VIO = VCC or GND, VCC = 5.5V
IOH = -1.0mA, VCC = 4.5V IOH = -100µA, VCC = 4.5V IOL = 4.0mA, VCC = 4.5V
Capacitance
SYMBOL CI CIO NOTES:
M AX 12 14
UNITS pF pF
TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
1. Typical derating 5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes.
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