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Details, datasheet, quote on part number:HM-6561/883
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Datasheet text preview:
TM
HM-6561/883
256 x 4 CMOS RAM
Description
The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On-chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The data inputs and outputs are multiplexed internally for common I/O bus compatibility. The HM-6561/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.
March 1997
Features
· This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. · Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max · Low Power Operation . . . . . . . . . . . . . .20mW/MHz Max · Fast Access Time . . . . . . . . . . . . . . . . . . . . . 200ns Max · Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min · TTL Compatible Input/Output · High Output Drive - 1 TTL Load · On-Chip Address Registers · Common Data In/Out · Three-State Output · Easy Microprocessor Interfacing
Ordering Information
P ACKAGE TEMPERATURE RANGE CERDIP -55oC to +125oC 220ns HM1-6561B/883 300ns HM1-6561/883 PKG. NO. F18.3
Pinout
HM-6561/883 (CERDIP) TOP VIEW
A3 A2 A1 A0 A5 A6 A7 G ND E 1 2 3 4 5 6 7 8 9 18 VCC 17 A4 16 W 15 S1 14 DQ3 13 DQ2 12 DQ1 11 DQ0 10 S2
PIN A E W S DQ
DESC RIPTION Address Input Chip Enable Write Enable Chip Select Data In/Out
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2990.1
117
HM-6561/883 Functional Diagram
A0 A1 A5 A6 A7 A LATCHED ADDRESS REGISTER 5 A 5 L D A Q LATCH L LATCH D L D A Q LATCH L D DQ3 A Q LATCH L A L W E S1 S2 A2 A3 A4 3 A 3 A A A GATED COLUMN DECODER AND DATA I / O G A DQ0 G 8 8 8 8 GATED ROW DECODER 32 x 32 MATRIX
32
DQ1
A
Q
DQ2
LATCHED ADDRESS REGISTER
NOTES : 1. All lines positive logic-active high. 2. Three-state Buffers: A high output active. 3. Data Latches: L high Q = D and Q latches on falling edge of L. 4. Addr ess Latches and Gated Decoders: Latch on falling edge of E and gate on falling edge of E.
6-118
HM-6561/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage . . . . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance CERD IP Package . . . . . . . . . . . . . . . . 74oC/W 18oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC JA JC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VCC - 2.0V to VCC Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max
TABLE 1. HM- 6561/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PA RAME TER Output Low Voltage SYMBOL V OL (NOTE 1) CONDITIONS VCC = 4.5V, IOL = 1.6mA VCC = 4.5V, IOH = -0.4mA VCC = 5.5V, VI = GND or VCC VCC = 5.5V, VIO = GND or VCC VCC = 2.0V, E = VCC, IO = 0mA, VCC = 5.5V, (Note 2), E = 1MHz, W = GND, VI = VCC or GND VCC = 5.5V, IO = 0mA, VI = VCC or GND GROUP A SUBGROUPS 1, 2, 3 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN M AX 0.4 UNITS V
Output High Voltage
VOH
1, 2, 3
2.4
-
V
Input Leakage Current
II
1, 2, 3
-1.0
+1.0
µA µA
Input/Output Leakage Current
IIOZ
1, 2, 3
-1.0
+1.0
Data Retention Supply Current
ICCDR
1, 2, 3
-55oC TA +125oC
-
10
µA
Operating Supply Current
ICCOP
1, 2, 3
-55oC TA +125oC
-
4
mA
Standby Supply Current
ICCSB
1, 2, 3
-55oC TA +125oC
-
10
µA
NOTES : 1. All voltages referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP.
6-119
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