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Details, datasheet, quote on part number:HM-6561
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Datasheet text preview:
TM
HM-6561
256 x 4 CMOS RAM
Description
The HM-6561 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On-chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The data inputs and outputs are multiplexed internally for common I/O bus com patibility. The HM-6561 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.
March 1997
Features
· Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max · Low Power Operation . . . . . . . . . . . . . .20mW/MHz Max · Fast Access Time . . . . . . . . . . . . . . . . . . . . . 200ns Max · Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min · TTL Compatible Input/Output · High Output Drive - 1 TTL Load · On-Chip Address Registers · Common Data In/Out · Three-State Output · Easy Microprocessor Interfacing
Ordering Information
P ACKAGE CERDIP TEMPERATURE RANGE -40oC to +85oC 220ns HM1-6561B-9 300ns HM1-6561-9 PKG. NO. F18.3
Pinout
HM-6561 (CERDIP) TOP VIEW
A3 A2 A1 A0 A5 A6 A7 G ND E 1 2 3 4 5 6 7 8 9 18 VCC 17 A4 16 W 15 S1 14 DQ3 13 DQ2 12 DQ1 11 DQ0 10 S2
PIN A E W S DQ
DESC RIPTION Address Input Chip Enable Write Enable Chip Select Data In/Out
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2991.1
1
HM-6561 Functional Diagram
A0 A1 A5 A6 A7 A LATCHED ADDRESS REGISTER 5 A 5 GATED ROW DECODER 32 x 32 MATRIX
32
L
G A G D
8
8
8
8
DQ0
A
Q
LATCH L LATCH D L D LATCH L D LATCH L
A
GATED COLUMN DECODER AND DATA I / O
DQ1
A
Q
A
DQ2
A
Q
A 3 A L A 3
DQ3
A
Q
LATCHED ADDRESS REGISTER
W E S1 S2 A2 A3 A4
NOTES : 1. All lines positive logic-active high. 2. Three-state Buffers: A high output active. 3. Data Latches: L high Q = D and Q latches on falling edge of L. 4. Addr ess Latches and Gated Decoders: Latch on falling edge of E and gate on falling edge of E.
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HM-6561
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage . . . . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance CERD IP Package . . . . . . . . . . . . . . . . 74oC/W 18oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC JA JC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-6561B-9, HM6561-9 . . . . . . . . . . . . . . . . . . . .-40oC to +85oC
DC Electrical Specifications VCC = 5V ± 10%; TA = -40oC to +85oC (HM-6561B-9, HM-6561-9)
LIMITS SYMBOL ICCSB ICCOP ICCDR VCCDR II IIOZ VIL V IH VOL VOH PARAMETER S tandby Supply Current Operating Supply Current (Note 1) Data Retention Supply Current Data Retention Supply Voltage Input Leakage Current Input/Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage MIN 2.0 -1.0 -1.0 -0.3 VCC -2.0 2.4 MAX 10 4 10 +1.0 +1.0 0.8 VCC +0.3 0.4 UNITS µA mA µA V µA µA V V V V VI = VCC or GND, VCC = 5.5V VIO = VCC or GND, VCC = 5.5V VCC = 4.5V VCC = 5.5V IO = 1.6mA, VCC = 4.5V IO = -0.4mA, VCC = 5.5V TEST CONDITIONS IO = 0mA, VI = VCC or GND, VCC = 5.5V E = 1MHz, IO = 0mA, V CC = 5.5V, VI = VCC or GND, W = GND VCC = 2.0V, IO = 0mA, VI = VCC or GND, E = VCC
Capacitance TA = +25oC
SYMBOL CI CIO NOTES: 1. Typical derating 1.5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes. PARAMETER Input Capacitance (Note 2) Input/Output Capacitance (Note 2) M AX 6 10 UNITS pF pF TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
6-3
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