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Details, datasheet, quote on part number:HM-6551/883
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Datasheet text preview:
TM
HM-6551/883
256 x 4 CMOS RAM
Description
The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The HM-6551/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.
March 1997
Features
· This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. · Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max · Low Power Operation . . . . . . . . . . . . . .20mW/MHz Max · Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 220ns Max · Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min · TTL Compatible Input/Output · High Output Drive - 1 TTL Load · Internal Latched Chip Select · High Noise Immunity · On-Chip Address Register · Latched Outputs · Three-State Output
Ordering Information
P ACKAGE CE RDIP TEMPERATURE RANGE -55oC to +125oC 220ns HM-6551B/883 300ns HM1-6551/883 PKG. NO. F22.4
Pinout
HM-6551/883 (CERDIP) TOP VIEW
A3 1 A2 2 A1 3 A0 4 A5 5 A6 6 A7 7 G ND 8 D0 9 Q0 10 D1 11 22 VCC 21 A4 20 W 19 S1 18 E 17 S2 16 Q3 15 D3 14 Q2 13 D2 12 Q1
PIN A E W S D Q
DESC RIPTION Address Input Chip Enable Write Enable Chip Select Data Input Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN
2988.1
101
HM-6551/883 Functional Diagram
A0 A1 A5 A6 A7 D0 D1 D2 D3 A LATC HED ADDRESS REGISTER 5 A 5 8 A A A A A E W S2 S1 L D SELECT Q LATCH LATCHED ADDRESS REGISTER GATED COLUMN DECODER AND DATA I/O D DATA OUTPUT Q D LATCHES D 3 A 3 L Q Q A Q2 A Q3 A 8 8 8 D Q A Q0 Q1 GATED RO W DECODER 32 32 x 32 MATRIX
A2
A3
A4
NOTES : 1. Select Latch: L Low Q = D and Q latches on rising edge of L. 2. Addr ess Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge of E. 3. All lines positive logic-active high. 4. Three-S tate Buffers: A high output active. 5. Data Latches: L High Q = D and Q latches on falling edge of L.
6-102
HM-6551/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance JA JC CERD IP Package . . . . . . . . . . . . . . . . 60oC/W 15oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1930 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max.
TABLE 1. HM- 6551/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETE R Output Low Voltage SYMBOL V OL (NOTE 1) CONDITIONS V CC = 4.5V IOL = 1.6mA VCC = 4.5V IOH = -0.4mA V CC = 5.5V, V I = GND or VCC V CC = 5.5 V, VO = GND or VCC V CC = 2.0V, E = VCC IO = 0mA, VI = VCC or GND VCC = 5.5V, (Note 2) E = 1MHz, IO = 0mA VI = VCC or GND V CC = 5.5V, IO = 0mA VI = VCC or GND GR OU P A SUBGROUPS 1, 2, 3 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN M AX 0.4 UNITS V
Output High Voltage
VOH
1, 2, 3
2.4
-
V µA µA µA
Input Leakage Current
II
1, 2, 3
-1.0
+1.0
Output Leakage Current Data Retention Supply Current
IOZ
1, 2, 3
-1.0
+1.0
ICCDR
1, 2, 3
-
10
Operating Supply Current
ICCOP
1, 2, 3
-55oC TA +125oC
-
4
mA
S tandby Supply Current
ICCSB
1, 2, 3
-55oC TA +125oC
-
10
µA
NOTES : 1. All voltages referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP.
103
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