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Details, datasheet, quote on part number:HM-6551
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Datasheet text preview:
TM
HM-6551
256 x 4 CMOS RAM
Description
The HM-6551 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The HM-6551 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed overtemperature.
March 1997
Features
· · · · · · · · · · · Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max Low Power Operation . . . . . . . . . . . . . .20mW/MHz Max Fast Access Time . . . . . . . . . . . . . . . . . . . . . 220ns Max Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min TTL Compatible Input/Output High Output Drive - 1 TTL Load Internal Latched Chip Select High Noise Immunity On-Chip Address Register Latched Outputs Three-State Output
Ordering Information
P ACKAGE Plastic DIP CERDIP TEMPERATURE RANGE -40oC to +85oC -40oC to +85oC 220ns HM3-6551B-9 HM1-6551B-9 300ns HM3-6551-9 HM1-6551-9 PKG. NO. E22.4 F22.4
Pinout
HM-6551 (PDIP, CERDIP) TOP VIEW
A3 1 A2 2 A1 3 A0 4 A5 5 A6 6 A7 7 G ND 8 D0 9 Q0 10 D1 11 22 VCC 21 A4 20 W 19 S1 18 E 17 S2 16 Q3 15 D3 14 Q2 13 D2 12 Q1
PIN A E W S D Q
DESC RIPTION Address Input Chip Enable Write E5able Chip Select Data Input Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2989.1
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HM-6551 Functional Diagram
A0 A1 A5 A6 A7 D0 D1 D2 D3 A LATCHED ADDRESS REGISTER 5 A 5 A A A A A GATED COLUMN DECODER AND DATA I/O D GATED RO W DECODER 32 32 x 32 MATRIX
8
8
8
8
D
Q Q A A A A
Q0 Q1 Q2 Q3
DAT A OUTPUT Q D LATCHES D Q L
3 A
3
E W S2 S1 L D SELECT Q LATCH
LATCHED ADDRESS REGISTER
A2
A3
A4
NOTES : 1. Select Latch: L Low Q = D and Q latches on rising edge of L. 2. Addr ess Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge of E. 3. All lines positive logic-active high. 4. Three-S tate Buffers: A high output active. 5. Data Latches: L High Q = D and Q latches on falling edge of L.
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HM-6551
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) CERD IP Package . . . . . . . . . . . . . . . . 60oC/W 15oC/W Plastic DIP Package . . . . . . . . . . . . . . 75oC/W N/A Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC JA JC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-6551B-9, HM-6551-9 . . . . . . . . . . . . . . . . . . . - 40oC to +85oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1930 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6551B-9, HM-6551-9)
LIMITS SYMBOL ICCSB ICCOP ICCDR VCCDR II I OZ VIL V IH VOL VOH PARAMETER S tandby Supply Current Operating Supply Current (Note 1) Data Retention Supply Current Data Retention Supply Voltage Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage MIN 2.0 -1.0 -1.0 -0.3 VCC -2.0 2.4 MAX 10 4 10 +1.0 +1.0 0.8 VCC +0.3 0.4 UNITS µA mA µA V µA µA V V V V VI = VCC or GND, VCC = 5.5V VO = VCC or GND, VCC = 5.5V VCC = 4.5V VCC = 5.5V IO = 1.6mA, VCC = 4.5V IO = -0.4mA, VCC = 4.5V TEST CONDITIONS IO = 0mA, VI = VCC or GND, VCC = 5.5V E = 1MHz, IO = 0mA, V CC = 5.5V, VI = VCC or GND, W = GND VCC = 2.0V, IO = 0mA, VI = VCC or GND, E = VCC
Capacitance TA = +25oC
SYMBOL CI CO NOTES: 1. Typical derating 1.5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes. PARAMETER Input Capacitance (Note 2) Output Capacitance (Note 2) M AX 6 10 UNITS pF pF TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
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